projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 794d15b2 SS |
1 | /* |
| 2 | * arch/arm/mach-mv78xx0/db78x00-bp-setup.c | |
| 3 | * | |
| 4 | * Marvell DB-78x00-BP Development Board Setup | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public | |
| 7 | * License version 2. This program is licensed "as is" without any | |
| 8 | * warranty of any kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 11 | #include <linux/kernel.h> | |
| 12 | #include <linux/init.h> | |
| 13 | #include <linux/platform_device.h> | |
| 14 | #include <linux/ata_platform.h> | |
| 15 | #include <linux/mv643xx_eth.h> | |
| 04185fc6 | 16 | #include <linux/ethtool.h> |
| a09e64fb | 17 | #include <mach/mv78xx0.h> |
| 794d15b2 SS |
18 | #include <asm/mach-types.h> |
| 19 | #include <asm/mach/arch.h> | |
| 20 | #include "common.h" | |
| 21 | ||
| 22 | static struct mv643xx_eth_platform_data db78x00_ge00_data = { | |
| ac840605 | 23 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), |
| 794d15b2 SS |
24 | }; |
| 25 | ||
| 26 | static struct mv643xx_eth_platform_data db78x00_ge01_data = { | |
| ac840605 | 27 | .phy_addr = MV643XX_ETH_PHY_ADDR(9), |
| 794d15b2 SS |
28 | }; |
| 29 | ||
| 30 | static struct mv643xx_eth_platform_data db78x00_ge10_data = { | |
| f1f54657 | 31 | .phy_addr = MV643XX_ETH_PHY_ADDR(10), |
| 794d15b2 SS |
32 | }; |
| 33 | ||
| 34 | static struct mv643xx_eth_platform_data db78x00_ge11_data = { | |
| f1f54657 | 35 | .phy_addr = MV643XX_ETH_PHY_ADDR(11), |
| 794d15b2 SS |
36 | }; |
| 37 | ||
| 38 | static struct mv_sata_platform_data db78x00_sata_data = { | |
| 39 | .n_ports = 2, | |
| 40 | }; | |
| 41 | ||
| 42 | static void __init db78x00_init(void) | |
| 43 | { | |
| 44 | /* | |
| 45 | * Basic MV78xx0 setup. Needs to be called early. | |
| 46 | */ | |
| 47 | mv78xx0_init(); | |
| 48 | ||
| 49 | /* | |
| 50 | * Partition on-chip peripherals between the two CPU cores. | |
| 51 | */ | |
| 52 | if (mv78xx0_core_index() == 0) { | |
| 53 | mv78xx0_ehci0_init(); | |
| 54 | mv78xx0_ehci1_init(); | |
| 55 | mv78xx0_ehci2_init(); | |
| 56 | mv78xx0_ge00_init(&db78x00_ge00_data); | |
| 57 | mv78xx0_ge01_init(&db78x00_ge01_data); | |
| 58 | mv78xx0_ge10_init(&db78x00_ge10_data); | |
| 59 | mv78xx0_ge11_init(&db78x00_ge11_data); | |
| 60 | mv78xx0_sata_init(&db78x00_sata_data); | |
| 61 | mv78xx0_uart0_init(); | |
| 62 | mv78xx0_uart2_init(); | |
| 63 | } else { | |
| 64 | mv78xx0_uart1_init(); | |
| 65 | mv78xx0_uart3_init(); | |
| 66 | } | |
| 67 | } | |
| 68 | ||
| 69 | static int __init db78x00_pci_init(void) | |
| 70 | { | |
| 71 | if (machine_is_db78x00_bp()) { | |
| 72 | /* | |
| 73 | * Assign the x16 PCIe slot on the board to CPU core | |
| 74 | * #0, and let CPU core #1 have the four x1 slots. | |
| 75 | */ | |
| 76 | if (mv78xx0_core_index() == 0) | |
| 77 | mv78xx0_pcie_init(0, 1); | |
| 78 | else | |
| 79 | mv78xx0_pcie_init(1, 0); | |
| 80 | } | |
| 81 | ||
| 82 | return 0; | |
| 83 | } | |
| 84 | subsys_initcall(db78x00_pci_init); | |
| 85 | ||
| 86 | MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") | |
| 87 | /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ | |
| 88 | .phys_io = MV78XX0_REGS_PHYS_BASE, | |
| 89 | .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc, | |
| 90 | .boot_params = 0x00000100, | |
| 91 | .init_machine = db78x00_init, | |
| 92 | .map_io = mv78xx0_map_io, | |
| 93 | .init_irq = mv78xx0_init_irq, | |
| 94 | .timer = &mv78xx0_timer, | |
| 95 | MACHINE_END |