Commit | Line | Data |
---|---|---|
794d15b2 SS |
1 | /* |
2 | * arch/arm/mach-mv78xx0/common.c | |
3 | * | |
4 | * Core functions for Marvell MV78xx0 SoCs | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/serial_8250.h> | |
794d15b2 | 15 | #include <linux/ata_platform.h> |
2f129bf4 | 16 | #include <linux/clk-provider.h> |
712424fd | 17 | #include <linux/ethtool.h> |
3c317d00 | 18 | #include <asm/hardware/cache-feroceon-l2.h> |
794d15b2 SS |
19 | #include <asm/mach/map.h> |
20 | #include <asm/mach/time.h> | |
c02cecb9 AB |
21 | #include <linux/platform_data/usb-ehci-orion.h> |
22 | #include <linux/platform_data/mtd-orion_nand.h> | |
6f088f1d | 23 | #include <plat/time.h> |
28a2b450 | 24 | #include <plat/common.h> |
45173d5e | 25 | #include <plat/addr-map.h> |
4c811b99 AB |
26 | #include "mv78xx0.h" |
27 | #include "bridge-regs.h" | |
794d15b2 SS |
28 | #include "common.h" |
29 | ||
28a2b450 | 30 | static int get_tclk(void); |
794d15b2 SS |
31 | |
32 | /***************************************************************************** | |
33 | * Common bits | |
34 | ****************************************************************************/ | |
35 | int mv78xx0_core_index(void) | |
36 | { | |
37 | u32 extra; | |
38 | ||
39 | /* | |
40 | * Read Extra Features register. | |
41 | */ | |
42 | __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra)); | |
43 | ||
44 | return !!(extra & 0x00004000); | |
45 | } | |
46 | ||
47 | static int get_hclk(void) | |
48 | { | |
49 | int hclk; | |
50 | ||
51 | /* | |
52 | * HCLK tick rate is configured by DEV_D[7:5] pins. | |
53 | */ | |
54 | switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { | |
55 | case 0: | |
56 | hclk = 166666667; | |
57 | break; | |
58 | case 1: | |
59 | hclk = 200000000; | |
60 | break; | |
61 | case 2: | |
62 | hclk = 266666667; | |
63 | break; | |
64 | case 3: | |
65 | hclk = 333333333; | |
66 | break; | |
67 | case 4: | |
68 | hclk = 400000000; | |
69 | break; | |
70 | default: | |
71 | panic("unknown HCLK PLL setting: %.8x\n", | |
72 | readl(SAMPLE_AT_RESET_LOW)); | |
73 | } | |
74 | ||
75 | return hclk; | |
76 | } | |
77 | ||
78 | static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) | |
79 | { | |
80 | u32 cfg; | |
81 | ||
82 | /* | |
83 | * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1 | |
84 | * PCLK/L2CLK by bits [19:14]. | |
85 | */ | |
86 | if (core_index == 0) { | |
87 | cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; | |
88 | } else { | |
89 | cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; | |
90 | } | |
91 | ||
92 | /* | |
93 | * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK | |
94 | * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6). | |
95 | */ | |
96 | *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1; | |
97 | ||
98 | /* | |
99 | * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK | |
100 | * ratio (1, 2, 3). | |
101 | */ | |
102 | *l2clk = *pclk / (((cfg >> 4) & 3) + 1); | |
103 | } | |
104 | ||
105 | static int get_tclk(void) | |
106 | { | |
2f129bf4 | 107 | int tclk_freq; |
794d15b2 SS |
108 | |
109 | /* | |
110 | * TCLK tick rate is configured by DEV_A[2:0] strap pins. | |
111 | */ | |
112 | switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { | |
113 | case 1: | |
2f129bf4 | 114 | tclk_freq = 166666667; |
794d15b2 SS |
115 | break; |
116 | case 3: | |
2f129bf4 | 117 | tclk_freq = 200000000; |
794d15b2 SS |
118 | break; |
119 | default: | |
120 | panic("unknown TCLK PLL setting: %.8x\n", | |
121 | readl(SAMPLE_AT_RESET_HIGH)); | |
122 | } | |
123 | ||
2f129bf4 | 124 | return tclk_freq; |
794d15b2 SS |
125 | } |
126 | ||
127 | ||
128 | /***************************************************************************** | |
129 | * I/O Address Mapping | |
130 | ****************************************************************************/ | |
131 | static struct map_desc mv78xx0_io_desc[] __initdata = { | |
132 | { | |
383b9961 | 133 | .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE, |
794d15b2 SS |
134 | .pfn = 0, |
135 | .length = MV78XX0_CORE_REGS_SIZE, | |
136 | .type = MT_DEVICE, | |
794d15b2 | 137 | }, { |
383b9961 | 138 | .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE, |
794d15b2 SS |
139 | .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), |
140 | .length = MV78XX0_REGS_SIZE, | |
141 | .type = MT_DEVICE, | |
142 | }, | |
143 | }; | |
144 | ||
145 | void __init mv78xx0_map_io(void) | |
146 | { | |
147 | unsigned long phys; | |
148 | ||
149 | /* | |
150 | * Map the right set of per-core registers depending on | |
151 | * which core we are running on. | |
152 | */ | |
153 | if (mv78xx0_core_index() == 0) { | |
154 | phys = MV78XX0_CORE0_REGS_PHYS_BASE; | |
155 | } else { | |
156 | phys = MV78XX0_CORE1_REGS_PHYS_BASE; | |
157 | } | |
158 | mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys); | |
159 | ||
160 | iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc)); | |
161 | } | |
162 | ||
163 | ||
2f129bf4 AL |
164 | /***************************************************************************** |
165 | * CLK tree | |
166 | ****************************************************************************/ | |
167 | static struct clk *tclk; | |
168 | ||
169 | static void __init clk_init(void) | |
170 | { | |
313a98fa | 171 | tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk()); |
4574b886 AL |
172 | |
173 | orion_clkdev_init(tclk); | |
2f129bf4 AL |
174 | } |
175 | ||
794d15b2 SS |
176 | /***************************************************************************** |
177 | * EHCI | |
178 | ****************************************************************************/ | |
794d15b2 SS |
179 | void __init mv78xx0_ehci0_init(void) |
180 | { | |
72053353 | 181 | orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA); |
794d15b2 SS |
182 | } |
183 | ||
184 | ||
185 | /***************************************************************************** | |
186 | * EHCI1 | |
187 | ****************************************************************************/ | |
794d15b2 SS |
188 | void __init mv78xx0_ehci1_init(void) |
189 | { | |
db33f4de | 190 | orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); |
794d15b2 SS |
191 | } |
192 | ||
193 | ||
194 | /***************************************************************************** | |
195 | * EHCI2 | |
196 | ****************************************************************************/ | |
794d15b2 SS |
197 | void __init mv78xx0_ehci2_init(void) |
198 | { | |
db33f4de | 199 | orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); |
794d15b2 SS |
200 | } |
201 | ||
202 | ||
203 | /***************************************************************************** | |
204 | * GE00 | |
205 | ****************************************************************************/ | |
794d15b2 SS |
206 | void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) |
207 | { | |
db33f4de | 208 | orion_ge00_init(eth_data, |
7e3819d8 | 209 | GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, |
58569aee APR |
210 | IRQ_MV78XX0_GE_ERR, |
211 | MV643XX_TX_CSUM_DEFAULT_LIMIT); | |
794d15b2 SS |
212 | } |
213 | ||
214 | ||
215 | /***************************************************************************** | |
216 | * GE01 | |
217 | ****************************************************************************/ | |
794d15b2 SS |
218 | void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) |
219 | { | |
db33f4de | 220 | orion_ge01_init(eth_data, |
7e3819d8 | 221 | GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, |
58569aee APR |
222 | NO_IRQ, |
223 | MV643XX_TX_CSUM_DEFAULT_LIMIT); | |
794d15b2 SS |
224 | } |
225 | ||
226 | ||
227 | /***************************************************************************** | |
228 | * GE10 | |
229 | ****************************************************************************/ | |
794d15b2 SS |
230 | void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) |
231 | { | |
712424fd LB |
232 | u32 dev, rev; |
233 | ||
712424fd LB |
234 | /* |
235 | * On the Z0, ge10 and ge11 are internally connected back | |
236 | * to back, and not brought out. | |
237 | */ | |
238 | mv78xx0_pcie_id(&dev, &rev); | |
239 | if (dev == MV78X00_Z0_DEV_ID) { | |
240 | eth_data->phy_addr = MV643XX_ETH_PHY_NONE; | |
241 | eth_data->speed = SPEED_1000; | |
242 | eth_data->duplex = DUPLEX_FULL; | |
243 | } | |
244 | ||
db33f4de | 245 | orion_ge10_init(eth_data, |
7e3819d8 | 246 | GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, |
452503eb | 247 | NO_IRQ); |
794d15b2 SS |
248 | } |
249 | ||
250 | ||
251 | /***************************************************************************** | |
252 | * GE11 | |
253 | ****************************************************************************/ | |
794d15b2 SS |
254 | void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) |
255 | { | |
712424fd LB |
256 | u32 dev, rev; |
257 | ||
712424fd LB |
258 | /* |
259 | * On the Z0, ge10 and ge11 are internally connected back | |
260 | * to back, and not brought out. | |
261 | */ | |
262 | mv78xx0_pcie_id(&dev, &rev); | |
263 | if (dev == MV78X00_Z0_DEV_ID) { | |
264 | eth_data->phy_addr = MV643XX_ETH_PHY_NONE; | |
265 | eth_data->speed = SPEED_1000; | |
266 | eth_data->duplex = DUPLEX_FULL; | |
267 | } | |
268 | ||
db33f4de | 269 | orion_ge11_init(eth_data, |
7e3819d8 | 270 | GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, |
452503eb | 271 | NO_IRQ); |
794d15b2 SS |
272 | } |
273 | ||
69359943 | 274 | /***************************************************************************** |
aac7ffa3 | 275 | * I2C |
69359943 | 276 | ****************************************************************************/ |
69359943 RV |
277 | void __init mv78xx0_i2c_init(void) |
278 | { | |
aac7ffa3 AL |
279 | orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8); |
280 | orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8); | |
69359943 | 281 | } |
794d15b2 SS |
282 | |
283 | /***************************************************************************** | |
284 | * SATA | |
285 | ****************************************************************************/ | |
794d15b2 SS |
286 | void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) |
287 | { | |
db33f4de | 288 | orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA); |
794d15b2 SS |
289 | } |
290 | ||
291 | ||
292 | /***************************************************************************** | |
293 | * UART0 | |
294 | ****************************************************************************/ | |
794d15b2 SS |
295 | void __init mv78xx0_uart0_init(void) |
296 | { | |
28a2b450 | 297 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
74c33576 | 298 | IRQ_MV78XX0_UART_0, tclk); |
794d15b2 SS |
299 | } |
300 | ||
301 | ||
302 | /***************************************************************************** | |
303 | * UART1 | |
304 | ****************************************************************************/ | |
794d15b2 SS |
305 | void __init mv78xx0_uart1_init(void) |
306 | { | |
28a2b450 | 307 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
74c33576 | 308 | IRQ_MV78XX0_UART_1, tclk); |
794d15b2 SS |
309 | } |
310 | ||
311 | ||
312 | /***************************************************************************** | |
313 | * UART2 | |
314 | ****************************************************************************/ | |
794d15b2 SS |
315 | void __init mv78xx0_uart2_init(void) |
316 | { | |
28a2b450 | 317 | orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, |
74c33576 | 318 | IRQ_MV78XX0_UART_2, tclk); |
794d15b2 SS |
319 | } |
320 | ||
794d15b2 SS |
321 | /***************************************************************************** |
322 | * UART3 | |
323 | ****************************************************************************/ | |
794d15b2 SS |
324 | void __init mv78xx0_uart3_init(void) |
325 | { | |
28a2b450 | 326 | orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, |
74c33576 | 327 | IRQ_MV78XX0_UART_3, tclk); |
794d15b2 SS |
328 | } |
329 | ||
794d15b2 SS |
330 | /***************************************************************************** |
331 | * Time handling | |
332 | ****************************************************************************/ | |
4ee1f6b5 LB |
333 | void __init mv78xx0_init_early(void) |
334 | { | |
335 | orion_time_set_base(TIMER_VIRT_BASE); | |
95b80e0a TP |
336 | if (mv78xx0_core_index() == 0) |
337 | mvebu_mbus_init("marvell,mv78xx0-mbus", | |
338 | BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ, | |
339 | DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ); | |
340 | else | |
341 | mvebu_mbus_init("marvell,mv78xx0-mbus", | |
342 | BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ, | |
343 | DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ); | |
4ee1f6b5 LB |
344 | } |
345 | ||
bd721ea7 | 346 | void __ref mv78xx0_timer_init(void) |
794d15b2 | 347 | { |
4ee1f6b5 LB |
348 | orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, |
349 | IRQ_MV78XX0_TIMER_1, get_tclk()); | |
794d15b2 SS |
350 | } |
351 | ||
794d15b2 SS |
352 | |
353 | /***************************************************************************** | |
354 | * General | |
355 | ****************************************************************************/ | |
cfdeb637 LB |
356 | static char * __init mv78xx0_id(void) |
357 | { | |
358 | u32 dev, rev; | |
359 | ||
360 | mv78xx0_pcie_id(&dev, &rev); | |
361 | ||
362 | if (dev == MV78X00_Z0_DEV_ID) { | |
363 | if (rev == MV78X00_REV_Z0) | |
364 | return "MV78X00-Z0"; | |
365 | else | |
366 | return "MV78X00-Rev-Unsupported"; | |
367 | } else if (dev == MV78100_DEV_ID) { | |
368 | if (rev == MV78100_REV_A0) | |
369 | return "MV78100-A0"; | |
662aeced LB |
370 | else if (rev == MV78100_REV_A1) |
371 | return "MV78100-A1"; | |
cfdeb637 LB |
372 | else |
373 | return "MV78100-Rev-Unsupported"; | |
374 | } else if (dev == MV78200_DEV_ID) { | |
375 | if (rev == MV78100_REV_A0) | |
376 | return "MV78200-A0"; | |
377 | else | |
378 | return "MV78200-Rev-Unsupported"; | |
379 | } else { | |
380 | return "Device-Unknown"; | |
381 | } | |
382 | } | |
383 | ||
794d15b2 SS |
384 | static int __init is_l2_writethrough(void) |
385 | { | |
386 | return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); | |
387 | } | |
388 | ||
389 | void __init mv78xx0_init(void) | |
390 | { | |
391 | int core_index; | |
392 | int hclk; | |
393 | int pclk; | |
394 | int l2clk; | |
794d15b2 SS |
395 | |
396 | core_index = mv78xx0_core_index(); | |
397 | hclk = get_hclk(); | |
398 | get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); | |
794d15b2 | 399 | |
cfdeb637 LB |
400 | printk(KERN_INFO "%s ", mv78xx0_id()); |
401 | printk("core #%d, ", core_index); | |
794d15b2 SS |
402 | printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); |
403 | printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); | |
404 | printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); | |
2f129bf4 | 405 | printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); |
794d15b2 | 406 | |
d3201ede AB |
407 | if (IS_ENABLED(CONFIG_CACHE_FEROCEON_L2)) |
408 | feroceon_l2_init(is_l2_writethrough()); | |
2f129bf4 AL |
409 | |
410 | /* Setup root of clk tree */ | |
411 | clk_init(); | |
794d15b2 | 412 | } |
9635f9cd | 413 | |
7b6d864b | 414 | void mv78xx0_restart(enum reboot_mode mode, const char *cmd) |
9635f9cd RK |
415 | { |
416 | /* | |
417 | * Enable soft reset to assert RSTOUTn. | |
418 | */ | |
419 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); | |
420 | ||
421 | /* | |
422 | * Assert soft reset. | |
423 | */ | |
424 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); | |
425 | ||
426 | while (1) | |
427 | ; | |
428 | } |