[linux-2.6-block.git] / arch / arm / mach-mv78xx0 / common.c

/*
 * arch/arm/mach-mv78xx0/common.c
 *
 * Core functions for Marvell MV78xx0 SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/ata_platform.h>
#include <linux/ethtool.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/mv78xx0.h>
#include <mach/bridge-regs.h>
#include <plat/cache-feroceon-l2.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"

static int get_tclk(void);

/*****************************************************************************
 * Common bits
 ****************************************************************************/
int mv78xx0_core_index(void)
{
	u32 extra;

	/*
	 * Read Extra Features register.
	 */
	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));

	return !!(extra & 0x00004000);
}

static int get_hclk(void)
{
	int hclk;

	/*
	 * HCLK tick rate is configured by DEV_D[7:5] pins.
	 */
	switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
	case 0:
		hclk = 166666667;
		break;
	case 1:
		hclk = 200000000;
		break;
	case 2:
		hclk = 266666667;
		break;
	case 3:
		hclk = 333333333;
		break;
	case 4:
		hclk = 400000000;
		break;
	default:
		panic("unknown HCLK PLL setting: %.8x\n",
			readl(SAMPLE_AT_RESET_LOW));
	}

	return hclk;
}

static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
{
	u32 cfg;

	/*
	 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
	 * PCLK/L2CLK by bits [19:14].
	 */
	if (core_index == 0) {
		cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
	} else {
		cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
	}

	/*
	 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
	 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
	 */
	*pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;

	/*
	 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
	 * ratio (1, 2, 3).
	 */
	*l2clk = *pclk / (((cfg >> 4) & 3) + 1);
}

static int get_tclk(void)
{
	int tclk;

	/*
	 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
	 */
	switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
	case 1:
		tclk = 166666667;
		break;
	case 3:
		tclk = 200000000;
		break;
	default:
		panic("unknown TCLK PLL setting: %.8x\n",
			readl(SAMPLE_AT_RESET_HIGH));
	}

	return tclk;
}


/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc mv78xx0_io_desc[] __initdata = {
	{
		.virtual	= MV78XX0_CORE_REGS_VIRT_BASE,
		.pfn		= 0,
		.length		= MV78XX0_CORE_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= MV78XX0_PCIE_IO_VIRT_BASE(0),
		.pfn		= __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
		.length		= MV78XX0_PCIE_IO_SIZE * 8,
		.type		= MT_DEVICE,
	}, {
		.virtual	= MV78XX0_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
		.length		= MV78XX0_REGS_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init mv78xx0_map_io(void)
{
	unsigned long phys;

	/*
	 * Map the right set of per-core registers depending on
	 * which core we are running on.
	 */
	if (mv78xx0_core_index() == 0) {
		phys = MV78XX0_CORE0_REGS_PHYS_BASE;
	} else {
		phys = MV78XX0_CORE1_REGS_PHYS_BASE;
	}
	mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);

	iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
}


/*****************************************************************************
 * EHCI
 ****************************************************************************/
void __init mv78xx0_ehci0_init(void)
{
	orion_ehci_init(&mv78xx0_mbus_dram_info,
			USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
}


/*****************************************************************************
 * EHCI1
 ****************************************************************************/
void __init mv78xx0_ehci1_init(void)
{
	orion_ehci_1_init(&mv78xx0_mbus_dram_info,
			  USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
}


/*****************************************************************************
 * EHCI2
 ****************************************************************************/
void __init mv78xx0_ehci2_init(void)
{
	orion_ehci_2_init(&mv78xx0_mbus_dram_info,
			  USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
}


/*****************************************************************************
 * GE00
 ****************************************************************************/
void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
			GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
			IRQ_MV78XX0_GE_ERR, get_tclk());
}


/*****************************************************************************
 * GE01
 ****************************************************************************/
void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
			GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
			NO_IRQ, get_tclk());
}


/*****************************************************************************
 * GE10
 ****************************************************************************/
void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
{
	u32 dev, rev;

	/*
	 * On the Z0, ge10 and ge11 are internally connected back
	 * to back, and not brought out.
	 */
	mv78xx0_pcie_id(&dev, &rev);
	if (dev == MV78X00_Z0_DEV_ID) {
		eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
		eth_data->speed = SPEED_1000;
		eth_data->duplex = DUPLEX_FULL;
	}

	orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
			GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
			NO_IRQ, get_tclk());
}


/*****************************************************************************
 * GE11
 ****************************************************************************/
void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
{
	u32 dev, rev;

	/*
	 * On the Z0, ge10 and ge11 are internally connected back
	 * to back, and not brought out.
	 */
	mv78xx0_pcie_id(&dev, &rev);
	if (dev == MV78X00_Z0_DEV_ID) {
		eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
		eth_data->speed = SPEED_1000;
		eth_data->duplex = DUPLEX_FULL;
	}

	orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
			GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
			NO_IRQ, get_tclk());
}

/*****************************************************************************
 * I2C
 ****************************************************************************/
void __init mv78xx0_i2c_init(void)
{
	orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
	orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
}

/*****************************************************************************
 * SATA
 ****************************************************************************/
void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
{
	orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
			SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
}


/*****************************************************************************
 * UART0
 ****************************************************************************/
void __init mv78xx0_uart0_init(void)
{
	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
			 IRQ_MV78XX0_UART_0, get_tclk());
}


/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init mv78xx0_uart1_init(void)
{
	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
			 IRQ_MV78XX0_UART_1, get_tclk());
}


/*****************************************************************************
 * UART2
 ****************************************************************************/
void __init mv78xx0_uart2_init(void)
{
	orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
			 IRQ_MV78XX0_UART_2, get_tclk());
}

/*****************************************************************************
 * UART3
 ****************************************************************************/
void __init mv78xx0_uart3_init(void)
{
	orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
			 IRQ_MV78XX0_UART_3, get_tclk());
}

/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init mv78xx0_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
}

static void mv78xx0_timer_init(void)
{
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_MV78XX0_TIMER_1, get_tclk());
}

struct sys_timer mv78xx0_timer = {
	.init = mv78xx0_timer_init,
};


/*****************************************************************************
 * General
 ****************************************************************************/
static char * __init mv78xx0_id(void)
{
	u32 dev, rev;

	mv78xx0_pcie_id(&dev, &rev);

	if (dev == MV78X00_Z0_DEV_ID) {
		if (rev == MV78X00_REV_Z0)
			return "MV78X00-Z0";
		else
			return "MV78X00-Rev-Unsupported";
	} else if (dev == MV78100_DEV_ID) {
		if (rev == MV78100_REV_A0)
			return "MV78100-A0";
		else if (rev == MV78100_REV_A1)
			return "MV78100-A1";
		else
			return "MV78100-Rev-Unsupported";
	} else if (dev == MV78200_DEV_ID) {
		if (rev == MV78100_REV_A0)
			return "MV78200-A0";
		else
			return "MV78200-Rev-Unsupported";
	} else {
		return "Device-Unknown";
	}
}

static int __init is_l2_writethrough(void)
{
	return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
}

void __init mv78xx0_init(void)
{
	int core_index;
	int hclk;
	int pclk;
	int l2clk;
	int tclk;

	core_index = mv78xx0_core_index();
	hclk = get_hclk();
	get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
	tclk = get_tclk();

	printk(KERN_INFO "%s ", mv78xx0_id());
	printk("core #%d, ", core_index);
	printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
	printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
	printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
	printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);

	mv78xx0_setup_cpu_mbus();

#ifdef CONFIG_CACHE_FEROCEON_L2
	feroceon_l2_init(is_l2_writethrough());
#endif
}
Commit	Line	Data
794d15b2 SS	1	/*
	2	* arch/arm/mach-mv78xx0/common.c
	3	*
	4	* Core functions for Marvell MV78xx0 SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/serial_8250.h>
	15	#include <linux/mbus.h>
794d15b2	16	#include <linux/ata_platform.h>
712424fd	17	#include <linux/ethtool.h>
794d15b2 SS	18	#include <asm/mach/map.h>
794d15b2 SS	19	#include <asm/mach/time.h>
a09e64fb	20	#include <mach/mv78xx0.h>
fdd8b079	21	#include <mach/bridge-regs.h>
6f088f1d	22	#include <plat/cache-feroceon-l2.h>
6f088f1d LB	23	#include <plat/orion_nand.h>
6f088f1d LB	24	#include <plat/time.h>
28a2b450	25	#include <plat/common.h>
794d15b2 SS	26	#include "common.h"
794d15b2 SS	27
28a2b450	28	static int get_tclk(void);
794d15b2 SS	29
	30	/*****************************************************************************
	31	* Common bits
	32	****************************************************************************/
	33	int mv78xx0_core_index(void)
	34	{
	35	u32 extra;
	36
	37	/*
	38	* Read Extra Features register.
	39	*/
	40	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
	41
	42	return !!(extra & 0x00004000);
	43	}
	44
	45	static int get_hclk(void)
	46	{
	47	int hclk;
	48
	49	/*
	50	* HCLK tick rate is configured by DEV_D[7:5] pins.
	51	*/
	52	switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
	53	case 0:
	54	hclk = 166666667;
	55	break;
	56	case 1:
	57	hclk = 200000000;
	58	break;
	59	case 2:
	60	hclk = 266666667;
	61	break;
	62	case 3:
	63	hclk = 333333333;
	64	break;
	65	case 4:
	66	hclk = 400000000;
	67	break;
	68	default:
	69	panic("unknown HCLK PLL setting: %.8x\n",
	70	readl(SAMPLE_AT_RESET_LOW));
	71	}
	72
	73	return hclk;
	74	}
	75
	76	static void get_pclk_l2clk(int hclk, int core_index, int pclk, int l2clk)
	77	{
	78	u32 cfg;
	79
	80	/*
	81	* Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
	82	* PCLK/L2CLK by bits [19:14].
	83	*/
	84	if (core_index == 0) {
	85	cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
	86	} else {
	87	cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
	88	}
	89
	90	/*
	91	* Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
	92	* ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
93	*/
94	pclk = ((u64)hclk (2 + (cfg & 0xf))) >> 1;
95
96	/*
97	* Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
98	* ratio (1, 2, 3).
99	*/
100	l2clk = pclk / (((cfg >> 4) & 3) + 1);
101	}
102
103	static int get_tclk(void)
104	{
105	int tclk;
106
107	/*
108	* TCLK tick rate is configured by DEV_A[2:0] strap pins.
109	*/
110	switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
111	case 1:
112	tclk = 166666667;
113	break;
114	case 3:
115	tclk = 200000000;
116	break;
117	default:
118	panic("unknown TCLK PLL setting: %.8x\n",
119	readl(SAMPLE_AT_RESET_HIGH));
120	}
121
122	return tclk;
123	}
124
125
126	/*****************************************************************************
127	* I/O Address Mapping
128	****************************************************************************/
129	static struct map_desc mv78xx0_io_desc[] __initdata = {
130	{
131	.virtual = MV78XX0_CORE_REGS_VIRT_BASE,
132	.pfn = 0,
133	.length = MV78XX0_CORE_REGS_SIZE,
134	.type = MT_DEVICE,
135	}, {
136	.virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
137	.pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
138	.length = MV78XX0_PCIE_IO_SIZE * 8,
139	.type = MT_DEVICE,
140	}, {
141	.virtual = MV78XX0_REGS_VIRT_BASE,
142	.pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
143	.length = MV78XX0_REGS_SIZE,
144	.type = MT_DEVICE,
145	},
146	};
147
148	void __init mv78xx0_map_io(void)
149	{
150	unsigned long phys;
151
152	/*
153	* Map the right set of per-core registers depending on
154	* which core we are running on.
155	*/
156	if (mv78xx0_core_index() == 0) {
157	phys = MV78XX0_CORE0_REGS_PHYS_BASE;
158	} else {
159	phys = MV78XX0_CORE1_REGS_PHYS_BASE;
160	}
161	mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
162
163	iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
164	}
165
166
167	/*****************************************************************************
168	* EHCI
169	****************************************************************************/
794d15b2 SS	170	void __init mv78xx0_ehci0_init(void)
794d15b2 SS	171	{
4fcd3f37 AL	172	orion_ehci_init(&mv78xx0_mbus_dram_info,
4fcd3f37 AL	173	USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
794d15b2 SS	174	}
	175
	176
	177	/*****************************************************************************
	178	* EHCI1
	179	****************************************************************************/
794d15b2 SS	180	void __init mv78xx0_ehci1_init(void)
794d15b2 SS	181	{
4fcd3f37 AL	182	orion_ehci_1_init(&mv78xx0_mbus_dram_info,
4fcd3f37 AL	183	USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
794d15b2 SS	184	}
	185
	186
	187	/*****************************************************************************
	188	* EHCI2
	189	****************************************************************************/
794d15b2 SS	190	void __init mv78xx0_ehci2_init(void)
794d15b2 SS	191	{
4fcd3f37 AL	192	orion_ehci_2_init(&mv78xx0_mbus_dram_info,
4fcd3f37 AL	193	USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
794d15b2 SS	194	}
	195
	196
	197	/*****************************************************************************
	198	* GE00
	199	****************************************************************************/
794d15b2 SS	200	void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	201	{
7e3819d8 AL	202	orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
	203	GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
	204	IRQ_MV78XX0_GE_ERR, get_tclk());
794d15b2 SS	205	}
	206
	207
	208	/*****************************************************************************
	209	* GE01
	210	****************************************************************************/
794d15b2 SS	211	void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	212	{
7e3819d8 AL	213	orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
	214	GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
	215	NO_IRQ, get_tclk());
794d15b2 SS	216	}
	217
	218
	219	/*****************************************************************************
	220	* GE10
	221	****************************************************************************/
794d15b2 SS	222	void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	223	{
712424fd LB	224	u32 dev, rev;
712424fd LB	225
712424fd LB	226	/*
	227	* On the Z0, ge10 and ge11 are internally connected back
	228	* to back, and not brought out.
	229	*/
	230	mv78xx0_pcie_id(&dev, &rev);
	231	if (dev == MV78X00_Z0_DEV_ID) {
	232	eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
	233	eth_data->speed = SPEED_1000;
	234	eth_data->duplex = DUPLEX_FULL;
	235	}
	236
7e3819d8 AL	237	orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
	238	GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
	239	NO_IRQ, get_tclk());
794d15b2 SS	240	}
	241
	242
	243	/*****************************************************************************
	244	* GE11
	245	****************************************************************************/
794d15b2 SS	246	void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	247	{
712424fd LB	248	u32 dev, rev;
712424fd LB	249
712424fd LB	250	/*
	251	* On the Z0, ge10 and ge11 are internally connected back
	252	* to back, and not brought out.
	253	*/
	254	mv78xx0_pcie_id(&dev, &rev);
	255	if (dev == MV78X00_Z0_DEV_ID) {
	256	eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
	257	eth_data->speed = SPEED_1000;
	258	eth_data->duplex = DUPLEX_FULL;
	259	}
	260
7e3819d8 AL	261	orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
	262	GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
	263	NO_IRQ, get_tclk());
794d15b2 SS	264	}
794d15b2 SS	265
69359943	266	/*****************************************************************************
aac7ffa3	267	* I2C
69359943	268	****************************************************************************/
69359943 RV	269	void __init mv78xx0_i2c_init(void)
69359943 RV	270	{
aac7ffa3 AL	271	orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
aac7ffa3 AL	272	orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
69359943	273	}
794d15b2 SS	274
	275	/*****************************************************************************
	276	* SATA
	277	****************************************************************************/
794d15b2 SS	278	void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
794d15b2 SS	279	{
9e613f8a AL	280	orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
9e613f8a AL	281	SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
794d15b2 SS	282	}
	283
	284
	285	/*****************************************************************************
	286	* UART0
	287	****************************************************************************/
794d15b2 SS	288	void __init mv78xx0_uart0_init(void)
794d15b2 SS	289	{
28a2b450 AL	290	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
28a2b450 AL	291	IRQ_MV78XX0_UART_0, get_tclk());
794d15b2 SS	292	}
	293
	294
	295	/*****************************************************************************
	296	* UART1
	297	****************************************************************************/
794d15b2 SS	298	void __init mv78xx0_uart1_init(void)
794d15b2 SS	299	{
28a2b450 AL	300	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
28a2b450 AL	301	IRQ_MV78XX0_UART_1, get_tclk());
794d15b2 SS	302	}
	303
	304
	305	/*****************************************************************************
	306	* UART2
	307	****************************************************************************/
794d15b2 SS	308	void __init mv78xx0_uart2_init(void)
794d15b2 SS	309	{
28a2b450 AL	310	orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
28a2b450 AL	311	IRQ_MV78XX0_UART_2, get_tclk());
794d15b2 SS	312	}
794d15b2 SS	313
794d15b2 SS	314	/*****************************************************************************
	315	* UART3
	316	****************************************************************************/
794d15b2 SS	317	void __init mv78xx0_uart3_init(void)
794d15b2 SS	318	{
28a2b450 AL	319	orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
28a2b450 AL	320	IRQ_MV78XX0_UART_3, get_tclk());
794d15b2 SS	321	}
794d15b2 SS	322
794d15b2 SS	323	/*****************************************************************************
	324	* Time handling
	325	****************************************************************************/
4ee1f6b5 LB	326	void __init mv78xx0_init_early(void)
	327	{
	328	orion_time_set_base(TIMER_VIRT_BASE);
	329	}
	330
794d15b2 SS	331	static void mv78xx0_timer_init(void)
794d15b2 SS	332	{
4ee1f6b5 LB	333	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
4ee1f6b5 LB	334	IRQ_MV78XX0_TIMER_1, get_tclk());
794d15b2 SS	335	}
	336
	337	struct sys_timer mv78xx0_timer = {
	338	.init = mv78xx0_timer_init,
	339	};
	340
	341
	342	/*****************************************************************************
	343	* General
	344	****************************************************************************/
cfdeb637 LB	345	static char * __init mv78xx0_id(void)
	346	{
	347	u32 dev, rev;
	348
	349	mv78xx0_pcie_id(&dev, &rev);
	350
	351	if (dev == MV78X00_Z0_DEV_ID) {
	352	if (rev == MV78X00_REV_Z0)
	353	return "MV78X00-Z0";
	354	else
	355	return "MV78X00-Rev-Unsupported";
	356	} else if (dev == MV78100_DEV_ID) {
	357	if (rev == MV78100_REV_A0)
	358	return "MV78100-A0";
662aeced LB	359	else if (rev == MV78100_REV_A1)
662aeced LB	360	return "MV78100-A1";
cfdeb637 LB	361	else
	362	return "MV78100-Rev-Unsupported";
	363	} else if (dev == MV78200_DEV_ID) {
	364	if (rev == MV78100_REV_A0)
	365	return "MV78200-A0";
	366	else
	367	return "MV78200-Rev-Unsupported";
	368	} else {
	369	return "Device-Unknown";
	370	}
	371	}
	372
794d15b2 SS	373	static int __init is_l2_writethrough(void)
	374	{
	375	return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
	376	}
	377
	378	void __init mv78xx0_init(void)
	379	{
	380	int core_index;
	381	int hclk;
	382	int pclk;
	383	int l2clk;
	384	int tclk;
	385
	386	core_index = mv78xx0_core_index();
	387	hclk = get_hclk();
	388	get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
	389	tclk = get_tclk();
	390
cfdeb637 LB	391	printk(KERN_INFO "%s ", mv78xx0_id());
cfdeb637 LB	392	printk("core #%d, ", core_index);
794d15b2 SS	393	printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
	394	printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
	395	printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
	396	printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
	397
	398	mv78xx0_setup_cpu_mbus();
	399
	400	#ifdef CONFIG_CACHE_FEROCEON_L2
	401	feroceon_l2_init(is_l2_writethrough());
	402	#endif
794d15b2	403	}