[linux-2.6-block.git] / arch / arm / mach-msm / irq-vic.c

/*
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <linux/timer.h>
#include <linux/irq.h>
#include <linux/io.h>

#include <asm/cacheflush.h>

#include <mach/hardware.h>

#include <mach/msm_iomap.h>

#include "smd_private.h"

enum {
	IRQ_DEBUG_SLEEP_INT_TRIGGER = 1U << 0,
	IRQ_DEBUG_SLEEP_INT = 1U << 1,
	IRQ_DEBUG_SLEEP_ABORT = 1U << 2,
	IRQ_DEBUG_SLEEP = 1U << 3,
	IRQ_DEBUG_SLEEP_REQUEST = 1U << 4,
};
static int msm_irq_debug_mask;
module_param_named(debug_mask, msm_irq_debug_mask, int,
		   S_IRUGO | S_IWUSR | S_IWGRP);

#define VIC_REG(off) (MSM_VIC_BASE + (off))
#define VIC_INT_TO_REG_ADDR(base, irq) (base + (irq / 32) * 4)
#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 3)

#define VIC_INT_SELECT0     VIC_REG(0x0000)  /* 1: FIQ, 0: IRQ */
#define VIC_INT_SELECT1     VIC_REG(0x0004)  /* 1: FIQ, 0: IRQ */
#define VIC_INT_SELECT2     VIC_REG(0x0008)  /* 1: FIQ, 0: IRQ */
#define VIC_INT_SELECT3     VIC_REG(0x000C)  /* 1: FIQ, 0: IRQ */
#define VIC_INT_EN0         VIC_REG(0x0010)
#define VIC_INT_EN1         VIC_REG(0x0014)
#define VIC_INT_EN2         VIC_REG(0x0018)
#define VIC_INT_EN3         VIC_REG(0x001C)
#define VIC_INT_ENCLEAR0    VIC_REG(0x0020)
#define VIC_INT_ENCLEAR1    VIC_REG(0x0024)
#define VIC_INT_ENCLEAR2    VIC_REG(0x0028)
#define VIC_INT_ENCLEAR3    VIC_REG(0x002C)
#define VIC_INT_ENSET0      VIC_REG(0x0030)
#define VIC_INT_ENSET1      VIC_REG(0x0034)
#define VIC_INT_ENSET2      VIC_REG(0x0038)
#define VIC_INT_ENSET3      VIC_REG(0x003C)
#define VIC_INT_TYPE0       VIC_REG(0x0040)  /* 1: EDGE, 0: LEVEL  */
#define VIC_INT_TYPE1       VIC_REG(0x0044)  /* 1: EDGE, 0: LEVEL  */
#define VIC_INT_TYPE2       VIC_REG(0x0048)  /* 1: EDGE, 0: LEVEL  */
#define VIC_INT_TYPE3       VIC_REG(0x004C)  /* 1: EDGE, 0: LEVEL  */
#define VIC_INT_POLARITY0   VIC_REG(0x0050)  /* 1: NEG, 0: POS */
#define VIC_INT_POLARITY1   VIC_REG(0x0054)  /* 1: NEG, 0: POS */
#define VIC_INT_POLARITY2   VIC_REG(0x0058)  /* 1: NEG, 0: POS */
#define VIC_INT_POLARITY3   VIC_REG(0x005C)  /* 1: NEG, 0: POS */
#define VIC_NO_PEND_VAL     VIC_REG(0x0060)

#if defined(CONFIG_ARCH_MSM_SCORPION)
#define VIC_NO_PEND_VAL_FIQ VIC_REG(0x0064)
#define VIC_INT_MASTEREN    VIC_REG(0x0068)  /* 1: IRQ, 2: FIQ     */
#define VIC_CONFIG          VIC_REG(0x006C)  /* 1: USE SC VIC */
#else
#define VIC_INT_MASTEREN    VIC_REG(0x0064)  /* 1: IRQ, 2: FIQ     */
#define VIC_PROTECTION      VIC_REG(0x006C)  /* 1: ENABLE          */
#define VIC_CONFIG          VIC_REG(0x0068)  /* 1: USE ARM1136 VIC */
#endif

#define VIC_IRQ_STATUS0     VIC_REG(0x0080)
#define VIC_IRQ_STATUS1     VIC_REG(0x0084)
#define VIC_IRQ_STATUS2     VIC_REG(0x0088)
#define VIC_IRQ_STATUS3     VIC_REG(0x008C)
#define VIC_FIQ_STATUS0     VIC_REG(0x0090)
#define VIC_FIQ_STATUS1     VIC_REG(0x0094)
#define VIC_FIQ_STATUS2     VIC_REG(0x0098)
#define VIC_FIQ_STATUS3     VIC_REG(0x009C)
#define VIC_RAW_STATUS0     VIC_REG(0x00A0)
#define VIC_RAW_STATUS1     VIC_REG(0x00A4)
#define VIC_RAW_STATUS2     VIC_REG(0x00A8)
#define VIC_RAW_STATUS3     VIC_REG(0x00AC)
#define VIC_INT_CLEAR0      VIC_REG(0x00B0)
#define VIC_INT_CLEAR1      VIC_REG(0x00B4)
#define VIC_INT_CLEAR2      VIC_REG(0x00B8)
#define VIC_INT_CLEAR3      VIC_REG(0x00BC)
#define VIC_SOFTINT0        VIC_REG(0x00C0)
#define VIC_SOFTINT1        VIC_REG(0x00C4)
#define VIC_SOFTINT2        VIC_REG(0x00C8)
#define VIC_SOFTINT3        VIC_REG(0x00CC)
#define VIC_IRQ_VEC_RD      VIC_REG(0x00D0)  /* pending int # */
#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4)  /* pending vector addr */
#define VIC_IRQ_VEC_WR      VIC_REG(0x00D8)

#if defined(CONFIG_ARCH_MSM_SCORPION)
#define VIC_FIQ_VEC_RD      VIC_REG(0x00DC)
#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0)
#define VIC_FIQ_VEC_WR      VIC_REG(0x00E4)
#define VIC_IRQ_IN_SERVICE  VIC_REG(0x00E8)
#define VIC_IRQ_IN_STACK    VIC_REG(0x00EC)
#define VIC_FIQ_IN_SERVICE  VIC_REG(0x00F0)
#define VIC_FIQ_IN_STACK    VIC_REG(0x00F4)
#define VIC_TEST_BUS_SEL    VIC_REG(0x00F8)
#define VIC_IRQ_CTRL_CONFIG VIC_REG(0x00FC)
#else
#define VIC_IRQ_IN_SERVICE  VIC_REG(0x00E0)
#define VIC_IRQ_IN_STACK    VIC_REG(0x00E4)
#define VIC_TEST_BUS_SEL    VIC_REG(0x00E8)
#endif

#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
#define VIC_VECTADDR(n)     VIC_REG(0x0400+((n) * 4))

#if defined(CONFIG_ARCH_MSM7X30)
#define VIC_NUM_REGS	    4
#else
#define VIC_NUM_REGS	    2
#endif

#if VIC_NUM_REGS == 2
#define DPRINT_REGS(base_reg, format, ...)	      			\
	printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__,		\
			readl(base_reg ## 0), readl(base_reg ## 1))
#define DPRINT_ARRAY(array, format, ...)				\
	printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__,		\
			array[0], array[1])
#elif VIC_NUM_REGS == 4
#define DPRINT_REGS(base_reg, format, ...) \
	printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__,	\
			readl(base_reg ## 0), readl(base_reg ## 1),	\
			readl(base_reg ## 2), readl(base_reg ## 3))
#define DPRINT_ARRAY(array, format, ...)				\
	printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__,	\
			array[0], array[1],				\
			array[2], array[3])
#else
#error "VIC_NUM_REGS set to illegal value"
#endif

static uint32_t msm_irq_smsm_wake_enable[2];
static struct {
	uint32_t int_en[2];
	uint32_t int_type;
	uint32_t int_polarity;
	uint32_t int_select;
} msm_irq_shadow_reg[VIC_NUM_REGS];
static uint32_t msm_irq_idle_disable[VIC_NUM_REGS];

#define SMSM_FAKE_IRQ (0xff)
static uint8_t msm_irq_to_smsm[NR_IRQS] = {
	[INT_MDDI_EXT] = 1,
	[INT_MDDI_PRI] = 2,
	[INT_MDDI_CLIENT] = 3,
	[INT_USB_OTG] = 4,

	[INT_PWB_I2C] = 5,
	[INT_SDC1_0] = 6,
	[INT_SDC1_1] = 7,
	[INT_SDC2_0] = 8,

	[INT_SDC2_1] = 9,
	[INT_ADSP_A9_A11] = 10,
	[INT_UART1] = 11,
	[INT_UART2] = 12,

	[INT_UART3] = 13,
	[INT_UART1_RX] = 14,
	[INT_UART2_RX] = 15,
	[INT_UART3_RX] = 16,

	[INT_UART1DM_IRQ] = 17,
	[INT_UART1DM_RX] = 18,
	[INT_KEYSENSE] = 19,
#if !defined(CONFIG_ARCH_MSM7X30)
	[INT_AD_HSSD] = 20,
#endif

	[INT_NAND_WR_ER_DONE] = 21,
	[INT_NAND_OP_DONE] = 22,
	[INT_TCHSCRN1] = 23,
	[INT_TCHSCRN2] = 24,

	[INT_TCHSCRN_SSBI] = 25,
	[INT_USB_HS] = 26,
	[INT_UART2DM_RX] = 27,
	[INT_UART2DM_IRQ] = 28,

	[INT_SDC4_1] = 29,
	[INT_SDC4_0] = 30,
	[INT_SDC3_1] = 31,
	[INT_SDC3_0] = 32,

	/* fake wakeup interrupts */
	[INT_GPIO_GROUP1] = SMSM_FAKE_IRQ,
	[INT_GPIO_GROUP2] = SMSM_FAKE_IRQ,
	[INT_A9_M2A_0] = SMSM_FAKE_IRQ,
	[INT_A9_M2A_1] = SMSM_FAKE_IRQ,
	[INT_A9_M2A_5] = SMSM_FAKE_IRQ,
	[INT_GP_TIMER_EXP] = SMSM_FAKE_IRQ,
	[INT_DEBUG_TIMER_EXP] = SMSM_FAKE_IRQ,
	[INT_ADSP_A11] = SMSM_FAKE_IRQ,
#ifdef CONFIG_ARCH_QSD8X50
	[INT_SIRC_0] = SMSM_FAKE_IRQ,
	[INT_SIRC_1] = SMSM_FAKE_IRQ,
#endif
};

static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
{
	int i;

	for (i = 0; i < VIC_NUM_REGS; i++)
		writel(val, base + (i * 4));
}

static void msm_irq_ack(unsigned int irq)
{
	void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, irq);
	irq = 1 << (irq & 31);
	writel(irq, reg);
}

static void msm_irq_mask(unsigned int irq)
{
	void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, irq);
	unsigned index = VIC_INT_TO_REG_INDEX(irq);
	uint32_t mask = 1UL << (irq & 31);
	int smsm_irq = msm_irq_to_smsm[irq];

	msm_irq_shadow_reg[index].int_en[0] &= ~mask;
	writel(mask, reg);
	if (smsm_irq == 0)
		msm_irq_idle_disable[index] &= ~mask;
	else {
		mask = 1UL << (smsm_irq - 1);
		msm_irq_smsm_wake_enable[0] &= ~mask;
	}
}

static void msm_irq_unmask(unsigned int irq)
{
	void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, irq);
	unsigned index = VIC_INT_TO_REG_INDEX(irq);
	uint32_t mask = 1UL << (irq & 31);
	int smsm_irq = msm_irq_to_smsm[irq];

	msm_irq_shadow_reg[index].int_en[0] |= mask;
	writel(mask, reg);

	if (smsm_irq == 0)
		msm_irq_idle_disable[index] |= mask;
	else {
		mask = 1UL << (smsm_irq - 1);
		msm_irq_smsm_wake_enable[0] |= mask;
	}
}

static int msm_irq_set_wake(unsigned int irq, unsigned int on)
{
	unsigned index = VIC_INT_TO_REG_INDEX(irq);
	uint32_t mask = 1UL << (irq & 31);
	int smsm_irq = msm_irq_to_smsm[irq];

	if (smsm_irq == 0) {
		printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", irq);
		return -EINVAL;
	}
	if (on)
		msm_irq_shadow_reg[index].int_en[1] |= mask;
	else
		msm_irq_shadow_reg[index].int_en[1] &= ~mask;

	if (smsm_irq == SMSM_FAKE_IRQ)
		return 0;

	mask = 1UL << (smsm_irq - 1);
	if (on)
		msm_irq_smsm_wake_enable[1] |= mask;
	else
		msm_irq_smsm_wake_enable[1] &= ~mask;
	return 0;
}

static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
{
	void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, irq);
	void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, irq);
	unsigned index = VIC_INT_TO_REG_INDEX(irq);
	int b = 1 << (irq & 31);
	uint32_t polarity;
	uint32_t type;

	polarity = msm_irq_shadow_reg[index].int_polarity;
	if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
		polarity |= b;
	if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
		polarity &= ~b;
	writel(polarity, preg);
	msm_irq_shadow_reg[index].int_polarity = polarity;

	type = msm_irq_shadow_reg[index].int_type;
	if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
		type |= b;
		irq_desc[irq].handle_irq = handle_edge_irq;
	}
	if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
		type &= ~b;
		irq_desc[irq].handle_irq = handle_level_irq;
	}
	writel(type, treg);
	msm_irq_shadow_reg[index].int_type = type;
	return 0;
}

static struct irq_chip msm_irq_chip = {
	.name      = "msm",
	.disable   = msm_irq_mask,
	.ack       = msm_irq_ack,
	.mask      = msm_irq_mask,
	.unmask    = msm_irq_unmask,
	.set_wake  = msm_irq_set_wake,
	.set_type  = msm_irq_set_type,
};

void __init msm_init_irq(void)
{
	unsigned n;

	/* select level interrupts */
	msm_irq_write_all_regs(VIC_INT_TYPE0, 0);

	/* select highlevel interrupts */
	msm_irq_write_all_regs(VIC_INT_POLARITY0, 0);

	/* select IRQ for all INTs */
	msm_irq_write_all_regs(VIC_INT_SELECT0, 0);

	/* disable all INTs */
	msm_irq_write_all_regs(VIC_INT_EN0, 0);

	/* don't use vic */
	writel(0, VIC_CONFIG);

	/* enable interrupt controller */
	writel(3, VIC_INT_MASTEREN);

	for (n = 0; n < NR_MSM_IRQS; n++) {
		set_irq_chip(n, &msm_irq_chip);
		set_irq_handler(n, handle_level_irq);
		set_irq_flags(n, IRQF_VALID);
	}
}
Commit	Line	Data
f9f3d313 GB	1	/*
	2	* Copyright (C) 2007 Google, Inc.
	3	* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
	4	*
	5	* This software is licensed under the terms of the GNU General Public
	6	* License version 2, as published by the Free Software Foundation, and
	7	* may be copied, distributed, and modified under those terms.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/module.h>
	18	#include <linux/sched.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/ptrace.h>
	21	#include <linux/timer.h>
	22	#include <linux/irq.h>
	23	#include <linux/io.h>
	24
	25	#include <asm/cacheflush.h>
	26
	27	#include <mach/hardware.h>
	28
	29	#include <mach/msm_iomap.h>
	30
	31	#include "smd_private.h"
	32
	33	enum {
	34	IRQ_DEBUG_SLEEP_INT_TRIGGER = 1U << 0,
	35	IRQ_DEBUG_SLEEP_INT = 1U << 1,
	36	IRQ_DEBUG_SLEEP_ABORT = 1U << 2,
	37	IRQ_DEBUG_SLEEP = 1U << 3,
	38	IRQ_DEBUG_SLEEP_REQUEST = 1U << 4,
	39	};
	40	static int msm_irq_debug_mask;
	41	module_param_named(debug_mask, msm_irq_debug_mask, int,
	42	S_IRUGO \| S_IWUSR \| S_IWGRP);
	43
	44	#define VIC_REG(off) (MSM_VIC_BASE + (off))
	45	#define VIC_INT_TO_REG_ADDR(base, irq) (base + (irq / 32) * 4)
	46	#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 3)
	47
	48	#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
	49	#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
	50	#define VIC_INT_SELECT2 VIC_REG(0x0008) /* 1: FIQ, 0: IRQ */
	51	#define VIC_INT_SELECT3 VIC_REG(0x000C) /* 1: FIQ, 0: IRQ */
	52	#define VIC_INT_EN0 VIC_REG(0x0010)
	53	#define VIC_INT_EN1 VIC_REG(0x0014)
	54	#define VIC_INT_EN2 VIC_REG(0x0018)
	55	#define VIC_INT_EN3 VIC_REG(0x001C)
	56	#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
	57	#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
	58	#define VIC_INT_ENCLEAR2 VIC_REG(0x0028)
	59	#define VIC_INT_ENCLEAR3 VIC_REG(0x002C)
	60	#define VIC_INT_ENSET0 VIC_REG(0x0030)
	61	#define VIC_INT_ENSET1 VIC_REG(0x0034)
	62	#define VIC_INT_ENSET2 VIC_REG(0x0038)
	63	#define VIC_INT_ENSET3 VIC_REG(0x003C)
	64	#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
65	#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
66	#define VIC_INT_TYPE2 VIC_REG(0x0048) /* 1: EDGE, 0: LEVEL */
67	#define VIC_INT_TYPE3 VIC_REG(0x004C) /* 1: EDGE, 0: LEVEL */
68	#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
69	#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
70	#define VIC_INT_POLARITY2 VIC_REG(0x0058) /* 1: NEG, 0: POS */
71	#define VIC_INT_POLARITY3 VIC_REG(0x005C) /* 1: NEG, 0: POS */
72	#define VIC_NO_PEND_VAL VIC_REG(0x0060)
73
74	#if defined(CONFIG_ARCH_MSM_SCORPION)
75	#define VIC_NO_PEND_VAL_FIQ VIC_REG(0x0064)
76	#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */
77	#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE SC VIC */
78	#else
79	#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
80	#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
81	#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
82	#endif
83
84	#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
85	#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
86	#define VIC_IRQ_STATUS2 VIC_REG(0x0088)
87	#define VIC_IRQ_STATUS3 VIC_REG(0x008C)
88	#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
89	#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
90	#define VIC_FIQ_STATUS2 VIC_REG(0x0098)
91	#define VIC_FIQ_STATUS3 VIC_REG(0x009C)
92	#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
93	#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
94	#define VIC_RAW_STATUS2 VIC_REG(0x00A8)
95	#define VIC_RAW_STATUS3 VIC_REG(0x00AC)
96	#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
97	#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
98	#define VIC_INT_CLEAR2 VIC_REG(0x00B8)
99	#define VIC_INT_CLEAR3 VIC_REG(0x00BC)
100	#define VIC_SOFTINT0 VIC_REG(0x00C0)
101	#define VIC_SOFTINT1 VIC_REG(0x00C4)
102	#define VIC_SOFTINT2 VIC_REG(0x00C8)
103	#define VIC_SOFTINT3 VIC_REG(0x00CC)
104	#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
105	#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
106	#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
107
108	#if defined(CONFIG_ARCH_MSM_SCORPION)
109	#define VIC_FIQ_VEC_RD VIC_REG(0x00DC)
110	#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0)
111	#define VIC_FIQ_VEC_WR VIC_REG(0x00E4)
112	#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E8)
113	#define VIC_IRQ_IN_STACK VIC_REG(0x00EC)
114	#define VIC_FIQ_IN_SERVICE VIC_REG(0x00F0)
115	#define VIC_FIQ_IN_STACK VIC_REG(0x00F4)
116	#define VIC_TEST_BUS_SEL VIC_REG(0x00F8)
117	#define VIC_IRQ_CTRL_CONFIG VIC_REG(0x00FC)
118	#else
119	#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
120	#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
121	#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
122	#endif
123
124	#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
125	#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
126
127	#if defined(CONFIG_ARCH_MSM7X30)
128	#define VIC_NUM_REGS 4
129	#else
130	#define VIC_NUM_REGS 2
131	#endif
132
133	#if VIC_NUM_REGS == 2
134	#define DPRINT_REGS(base_reg, format, ...) \
135	printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
136	readl(base_reg ## 0), readl(base_reg ## 1))
137	#define DPRINT_ARRAY(array, format, ...) \
138	printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
139	array[0], array[1])
140	#elif VIC_NUM_REGS == 4
141	#define DPRINT_REGS(base_reg, format, ...) \
142	printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
143	readl(base_reg ## 0), readl(base_reg ## 1), \
144	readl(base_reg ## 2), readl(base_reg ## 3))
145	#define DPRINT_ARRAY(array, format, ...) \
146	printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
147	array[0], array[1], \
148	array[2], array[3])
149	#else
150	#error "VIC_NUM_REGS set to illegal value"
151	#endif
152
153	static uint32_t msm_irq_smsm_wake_enable[2];
154	static struct {
155	uint32_t int_en[2];
156	uint32_t int_type;
157	uint32_t int_polarity;
158	uint32_t int_select;
159	} msm_irq_shadow_reg[VIC_NUM_REGS];
160	static uint32_t msm_irq_idle_disable[VIC_NUM_REGS];
161
162	#define SMSM_FAKE_IRQ (0xff)
163	static uint8_t msm_irq_to_smsm[NR_IRQS] = {
164	[INT_MDDI_EXT] = 1,
165	[INT_MDDI_PRI] = 2,
166	[INT_MDDI_CLIENT] = 3,
167	[INT_USB_OTG] = 4,
168
169	[INT_PWB_I2C] = 5,
170	[INT_SDC1_0] = 6,
171	[INT_SDC1_1] = 7,
172	[INT_SDC2_0] = 8,
173
174	[INT_SDC2_1] = 9,
175	[INT_ADSP_A9_A11] = 10,
176	[INT_UART1] = 11,
177	[INT_UART2] = 12,
178
179	[INT_UART3] = 13,
180	[INT_UART1_RX] = 14,
181	[INT_UART2_RX] = 15,
182	[INT_UART3_RX] = 16,
183
184	[INT_UART1DM_IRQ] = 17,
185	[INT_UART1DM_RX] = 18,
186	[INT_KEYSENSE] = 19,
187	#if !defined(CONFIG_ARCH_MSM7X30)
188	[INT_AD_HSSD] = 20,
189	#endif
190
191	[INT_NAND_WR_ER_DONE] = 21,
192	[INT_NAND_OP_DONE] = 22,
193	[INT_TCHSCRN1] = 23,
194	[INT_TCHSCRN2] = 24,
195
196	[INT_TCHSCRN_SSBI] = 25,
197	[INT_USB_HS] = 26,
198	[INT_UART2DM_RX] = 27,
199	[INT_UART2DM_IRQ] = 28,
200
201	[INT_SDC4_1] = 29,
202	[INT_SDC4_0] = 30,
203	[INT_SDC3_1] = 31,
204	[INT_SDC3_0] = 32,
205
206	/* fake wakeup interrupts */
207	[INT_GPIO_GROUP1] = SMSM_FAKE_IRQ,
208	[INT_GPIO_GROUP2] = SMSM_FAKE_IRQ,
209	[INT_A9_M2A_0] = SMSM_FAKE_IRQ,
210	[INT_A9_M2A_1] = SMSM_FAKE_IRQ,
211	[INT_A9_M2A_5] = SMSM_FAKE_IRQ,
212	[INT_GP_TIMER_EXP] = SMSM_FAKE_IRQ,
213	[INT_DEBUG_TIMER_EXP] = SMSM_FAKE_IRQ,
214	[INT_ADSP_A11] = SMSM_FAKE_IRQ,
215	#ifdef CONFIG_ARCH_QSD8X50
216	[INT_SIRC_0] = SMSM_FAKE_IRQ,
217	[INT_SIRC_1] = SMSM_FAKE_IRQ,
218	#endif
219	};
220
221	static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
222	{
223	int i;
224
225	for (i = 0; i < VIC_NUM_REGS; i++)
226	writel(val, base + (i * 4));
227	}
228
229	static void msm_irq_ack(unsigned int irq)
230	{
231	void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, irq);
232	irq = 1 << (irq & 31);
233	writel(irq, reg);
234	}
235
236	static void msm_irq_mask(unsigned int irq)
237	{
238	void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, irq);
239	unsigned index = VIC_INT_TO_REG_INDEX(irq);
240	uint32_t mask = 1UL << (irq & 31);
241	int smsm_irq = msm_irq_to_smsm[irq];
242
243	msm_irq_shadow_reg[index].int_en[0] &= ~mask;
244	writel(mask, reg);
245	if (smsm_irq == 0)
246	msm_irq_idle_disable[index] &= ~mask;
247	else {
248	mask = 1UL << (smsm_irq - 1);
249	msm_irq_smsm_wake_enable[0] &= ~mask;
250	}
251	}
252
253	static void msm_irq_unmask(unsigned int irq)
254	{
255	void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, irq);
256	unsigned index = VIC_INT_TO_REG_INDEX(irq);
257	uint32_t mask = 1UL << (irq & 31);
258	int smsm_irq = msm_irq_to_smsm[irq];
259
260	msm_irq_shadow_reg[index].int_en[0] \|= mask;
261	writel(mask, reg);
262
263	if (smsm_irq == 0)
264	msm_irq_idle_disable[index] \|= mask;
265	else {
266	mask = 1UL << (smsm_irq - 1);
267	msm_irq_smsm_wake_enable[0] \|= mask;
268	}
269	}
270
271	static int msm_irq_set_wake(unsigned int irq, unsigned int on)
272	{
273	unsigned index = VIC_INT_TO_REG_INDEX(irq);
274	uint32_t mask = 1UL << (irq & 31);
275	int smsm_irq = msm_irq_to_smsm[irq];
276
277	if (smsm_irq == 0) {
278	printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", irq);
279	return -EINVAL;
280	}
281	if (on)
282	msm_irq_shadow_reg[index].int_en[1] \|= mask;
283	else
284	msm_irq_shadow_reg[index].int_en[1] &= ~mask;
285
286	if (smsm_irq == SMSM_FAKE_IRQ)
287	return 0;
288
289	mask = 1UL << (smsm_irq - 1);
290	if (on)
291	msm_irq_smsm_wake_enable[1] \|= mask;
292	else
293	msm_irq_smsm_wake_enable[1] &= ~mask;
294	return 0;
295	}
296
297	static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
298	{
299	void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, irq);
300	void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, irq);
301	unsigned index = VIC_INT_TO_REG_INDEX(irq);
302	int b = 1 << (irq & 31);
303	uint32_t polarity;
304	uint32_t type;
305
306	polarity = msm_irq_shadow_reg[index].int_polarity;
307	if (flow_type & (IRQF_TRIGGER_FALLING \| IRQF_TRIGGER_LOW))
308	polarity \|= b;
309	if (flow_type & (IRQF_TRIGGER_RISING \| IRQF_TRIGGER_HIGH))
310	polarity &= ~b;
311	writel(polarity, preg);
312	msm_irq_shadow_reg[index].int_polarity = polarity;
313
314	type = msm_irq_shadow_reg[index].int_type;
315	if (flow_type & (IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING)) {
316	type \|= b;
317	irq_desc[irq].handle_irq = handle_edge_irq;
318	}
319	if (flow_type & (IRQF_TRIGGER_HIGH \| IRQF_TRIGGER_LOW)) {
320	type &= ~b;
321	irq_desc[irq].handle_irq = handle_level_irq;
322	}
323	writel(type, treg);
324	msm_irq_shadow_reg[index].int_type = type;
325	return 0;
326	}
327
328	static struct irq_chip msm_irq_chip = {
329	.name = "msm",
330	.disable = msm_irq_mask,
331	.ack = msm_irq_ack,
332	.mask = msm_irq_mask,
333	.unmask = msm_irq_unmask,
334	.set_wake = msm_irq_set_wake,
335	.set_type = msm_irq_set_type,
336	};
337
338	void __init msm_init_irq(void)
339	{
340	unsigned n;
341
342	/* select level interrupts */
343	msm_irq_write_all_regs(VIC_INT_TYPE0, 0);
344
345	/* select highlevel interrupts */
346	msm_irq_write_all_regs(VIC_INT_POLARITY0, 0);
347
348	/* select IRQ for all INTs */
349	msm_irq_write_all_regs(VIC_INT_SELECT0, 0);
350
351	/* disable all INTs */
352	msm_irq_write_all_regs(VIC_INT_EN0, 0);
353
354	/* don't use vic */
355	writel(0, VIC_CONFIG);
356
357	/* enable interrupt controller */
358	writel(3, VIC_INT_MASTEREN);
359
360	for (n = 0; n < NR_MSM_IRQS; n++) {
361	set_irq_chip(n, &msm_irq_chip);
362	set_irq_handler(n, handle_level_irq);
363	set_irq_flags(n, IRQF_VALID);
364	}
365	}