Commit | Line | Data |
---|---|---|
2f7e8fae HZ |
1 | /* |
2 | * linux/arch/arm/mach-mmp/mmp2.c | |
3 | * | |
4 | * code name MMP2 | |
5 | * | |
6 | * Copyright (C) 2009 Marvell International Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/io.h> | |
17 | ||
66b19647 HZ |
18 | #include <asm/hardware/cache-tauros2.h> |
19 | ||
4d4a339d | 20 | #include <asm/mach/time.h> |
2f7e8fae HZ |
21 | #include <mach/addr-map.h> |
22 | #include <mach/regs-apbc.h> | |
23 | #include <mach/regs-apmu.h> | |
24 | #include <mach/cputype.h> | |
25 | #include <mach/irqs.h> | |
f4557870 | 26 | #include <mach/dma.h> |
2f7e8fae | 27 | #include <mach/mfp.h> |
16144bfb | 28 | #include <mach/gpio.h> |
2f7e8fae | 29 | #include <mach/devices.h> |
2728701d | 30 | #include <mach/mmp2.h> |
2f7e8fae HZ |
31 | |
32 | #include "common.h" | |
33 | #include "clock.h" | |
34 | ||
35 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) | |
36 | ||
16144bfb HZ |
37 | #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c) |
38 | ||
247b4592 | 39 | static struct mfp_addr_map mmp2_addr_map[] __initdata = { |
7f39403c HZ |
40 | |
41 | MFP_ADDR_X(GPIO0, GPIO58, 0x54), | |
42 | MFP_ADDR_X(GPIO59, GPIO73, 0x280), | |
43 | MFP_ADDR_X(GPIO74, GPIO101, 0x170), | |
44 | ||
45 | MFP_ADDR(GPIO102, 0x0), | |
46 | MFP_ADDR(GPIO103, 0x4), | |
47 | MFP_ADDR(GPIO104, 0x1fc), | |
48 | MFP_ADDR(GPIO105, 0x1f8), | |
49 | MFP_ADDR(GPIO106, 0x1f4), | |
50 | MFP_ADDR(GPIO107, 0x1f0), | |
51 | MFP_ADDR(GPIO108, 0x21c), | |
52 | MFP_ADDR(GPIO109, 0x218), | |
53 | MFP_ADDR(GPIO110, 0x214), | |
54 | MFP_ADDR(GPIO111, 0x200), | |
55 | MFP_ADDR(GPIO112, 0x244), | |
56 | MFP_ADDR(GPIO113, 0x25c), | |
57 | MFP_ADDR(GPIO114, 0x164), | |
58 | MFP_ADDR_X(GPIO115, GPIO122, 0x260), | |
59 | ||
60 | MFP_ADDR(GPIO123, 0x148), | |
61 | MFP_ADDR_X(GPIO124, GPIO141, 0xc), | |
62 | ||
63 | MFP_ADDR(GPIO142, 0x8), | |
64 | MFP_ADDR_X(GPIO143, GPIO151, 0x220), | |
65 | MFP_ADDR_X(GPIO152, GPIO153, 0x248), | |
66 | MFP_ADDR_X(GPIO154, GPIO155, 0x254), | |
67 | MFP_ADDR_X(GPIO156, GPIO159, 0x14c), | |
68 | ||
69 | MFP_ADDR(GPIO160, 0x250), | |
70 | MFP_ADDR(GPIO161, 0x210), | |
71 | MFP_ADDR(GPIO162, 0x20c), | |
72 | MFP_ADDR(GPIO163, 0x208), | |
73 | MFP_ADDR(GPIO164, 0x204), | |
74 | MFP_ADDR(GPIO165, 0x1ec), | |
75 | MFP_ADDR(GPIO166, 0x1e8), | |
76 | MFP_ADDR(GPIO167, 0x1e4), | |
77 | MFP_ADDR(GPIO168, 0x1e0), | |
78 | ||
79 | MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140), | |
80 | MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc), | |
81 | ||
247b4592 | 82 | MFP_ADDR(PMIC_INT, 0x2c4), |
7f39403c | 83 | MFP_ADDR(CLK_REQ, 0x160), |
247b4592 HZ |
84 | |
85 | MFP_ADDR_END, | |
86 | }; | |
87 | ||
df0c3824 HZ |
88 | void mmp2_clear_pmic_int(void) |
89 | { | |
90 | unsigned long mfpr_pmic, data; | |
91 | ||
92 | mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4; | |
93 | data = __raw_readl(mfpr_pmic); | |
94 | __raw_writel(data | (1 << 6), mfpr_pmic); | |
95 | __raw_writel(data, mfpr_pmic); | |
96 | } | |
97 | ||
16144bfb HZ |
98 | static void __init mmp2_init_gpio(void) |
99 | { | |
100 | int i; | |
101 | ||
102 | /* enable GPIO clock */ | |
103 | __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO); | |
104 | ||
105 | /* unmask GPIO edge detection for all 6 banks -- APMASKx */ | |
106 | for (i = 0; i < 6; i++) | |
107 | __raw_writel(0xffffffff, APMASK(i)); | |
108 | ||
109 | pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL); | |
110 | } | |
111 | ||
112 | void __init mmp2_init_irq(void) | |
113 | { | |
114 | mmp2_init_icu(); | |
115 | mmp2_init_gpio(); | |
116 | } | |
117 | ||
2f7e8fae HZ |
118 | /* APB peripheral clocks */ |
119 | static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); | |
120 | static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); | |
121 | static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); | |
122 | static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); | |
123 | static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); | |
124 | static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); | |
125 | static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); | |
126 | static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); | |
127 | static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); | |
128 | static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); | |
129 | static APBC_CLK(rtc, MMP2_RTC, 0, 32768); | |
130 | ||
131 | static APMU_CLK(nand, NAND, 0xbf, 100000000); | |
132 | ||
133 | static struct clk_lookup mmp2_clkregs[] = { | |
134 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | |
135 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | |
136 | INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), | |
137 | INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), | |
138 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), | |
139 | INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), | |
140 | INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), | |
141 | INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), | |
142 | INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), | |
143 | INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), | |
144 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | |
145 | }; | |
146 | ||
147 | static int __init mmp2_init(void) | |
148 | { | |
149 | if (cpu_is_mmp2()) { | |
66b19647 HZ |
150 | #ifdef CONFIG_CACHE_TAUROS2 |
151 | tauros2_init(); | |
152 | #endif | |
2f7e8fae | 153 | mfp_init_base(MFPR_VIRT_BASE); |
247b4592 | 154 | mfp_init_addr(mmp2_addr_map); |
f4557870 | 155 | pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); |
e5988636 | 156 | clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); |
2f7e8fae HZ |
157 | } |
158 | ||
159 | return 0; | |
160 | } | |
161 | postcore_initcall(mmp2_init); | |
162 | ||
4d4a339d EM |
163 | static void __init mmp2_timer_init(void) |
164 | { | |
165 | unsigned long clk_rst; | |
166 | ||
167 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); | |
168 | ||
169 | /* | |
170 | * enable bus/functional clock, enable 6.5MHz (divider 4), | |
171 | * release reset | |
172 | */ | |
173 | clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); | |
174 | __raw_writel(clk_rst, APBC_MMP2_TIMERS); | |
175 | ||
176 | timer_init(IRQ_MMP2_TIMER1); | |
177 | } | |
178 | ||
179 | struct sys_timer mmp2_timer = { | |
180 | .init = mmp2_timer_init, | |
181 | }; | |
182 | ||
2f7e8fae HZ |
183 | /* on-chip devices */ |
184 | MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); | |
185 | MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); | |
186 | MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23); | |
187 | MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19); | |
188 | MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70); | |
189 | MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70); | |
190 | MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70); | |
191 | MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); | |
192 | MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); | |
193 | MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); | |
194 | MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); | |
195 |