projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 2f7e8fae HZ |
1 | /* |
| 2 | * linux/arch/arm/mach-mmp/mmp2.c | |
| 3 | * | |
| 4 | * code name MMP2 | |
| 5 | * | |
| 6 | * Copyright (C) 2009 Marvell International Ltd. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #include <linux/module.h> | |
| 14 | #include <linux/kernel.h> | |
| 15 | #include <linux/init.h> | |
| 16 | #include <linux/io.h> | |
| 17 | ||
| 18 | #include <mach/addr-map.h> | |
| 19 | #include <mach/regs-apbc.h> | |
| 20 | #include <mach/regs-apmu.h> | |
| 21 | #include <mach/cputype.h> | |
| 22 | #include <mach/irqs.h> | |
| 23 | #include <mach/mfp.h> | |
| 24 | #include <mach/devices.h> | |
| 25 | ||
| 26 | #include "common.h" | |
| 27 | #include "clock.h" | |
| 28 | ||
| 29 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) | |
| 30 | ||
| 247b4592 HZ |
31 | static struct mfp_addr_map mmp2_addr_map[] __initdata = { |
| 32 | MFP_ADDR(PMIC_INT, 0x2c4), | |
| 33 | ||
| 34 | MFP_ADDR_END, | |
| 35 | }; | |
| 36 | ||
| 2f7e8fae HZ |
37 | /* APB peripheral clocks */ |
| 38 | static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); | |
| 39 | static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); | |
| 40 | static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); | |
| 41 | static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); | |
| 42 | static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); | |
| 43 | static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); | |
| 44 | static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); | |
| 45 | static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); | |
| 46 | static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); | |
| 47 | static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); | |
| 48 | static APBC_CLK(rtc, MMP2_RTC, 0, 32768); | |
| 49 | ||
| 50 | static APMU_CLK(nand, NAND, 0xbf, 100000000); | |
| 51 | ||
| 52 | static struct clk_lookup mmp2_clkregs[] = { | |
| 53 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | |
| 54 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | |
| 55 | INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), | |
| 56 | INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), | |
| 57 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), | |
| 58 | INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), | |
| 59 | INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), | |
| 60 | INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), | |
| 61 | INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), | |
| 62 | INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), | |
| 63 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | |
| 64 | }; | |
| 65 | ||
| 66 | static int __init mmp2_init(void) | |
| 67 | { | |
| 68 | if (cpu_is_mmp2()) { | |
| 69 | mfp_init_base(MFPR_VIRT_BASE); | |
| 247b4592 | 70 | mfp_init_addr(mmp2_addr_map); |
| 2f7e8fae HZ |
71 | clks_register(ARRAY_AND_SIZE(mmp2_clkregs)); |
| 72 | } | |
| 73 | ||
| 74 | return 0; | |
| 75 | } | |
| 76 | postcore_initcall(mmp2_init); | |
| 77 | ||
| 78 | /* on-chip devices */ | |
| 79 | MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); | |
| 80 | MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); | |
| 81 | MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23); | |
| 82 | MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19); | |
| 83 | MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70); | |
| 84 | MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70); | |
| 85 | MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70); | |
| 86 | MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); | |
| 87 | MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); | |
| 88 | MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); | |
| 89 | MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); | |
| 90 |