projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| e861cfbe | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 19d95e1a | 2 | /* |
| f5c42271 | 3 | * Platform support for LPC32xx SoC |
| 19d95e1a KW |
4 | * |
| 5 | * Author: Kevin Wells <kevin.wells@nxp.com> | |
| 6 | * | |
| f5c42271 | 7 | * Copyright (C) 2012 Roland Stigge <stigge@antcom.de> |
| 19d95e1a | 8 | * Copyright (C) 2010 NXP Semiconductors |
| 19d95e1a KW |
9 | */ |
| 10 | ||
| 291dd71f | 11 | #include <linux/amba/pl08x.h> |
| 5b941238 | 12 | #include <linux/mtd/lpc32xx_mlc.h> |
| a1e65c28 VZ |
13 | #include <linux/mtd/lpc32xx_slc.h> |
| 14 | #include <linux/of_platform.h> | |
| 19d95e1a | 15 | |
| 19d95e1a | 16 | #include <asm/mach/arch.h> |
| 19d95e1a KW |
17 | #include "common.h" |
| 18 | ||
| d807af47 RS |
19 | static struct pl08x_channel_data pl08x_slave_channels[] = { |
| 20 | { | |
| 21 | .bus_id = "nand-slc", | |
| 22 | .min_signal = 1, /* SLC NAND Flash */ | |
| 23 | .max_signal = 1, | |
| 24 | .periph_buses = PL08X_AHB1, | |
| 25 | }, | |
| 26 | { | |
| 27 | .bus_id = "nand-mlc", | |
| 28 | .min_signal = 12, /* MLC NAND Flash */ | |
| 29 | .max_signal = 12, | |
| 30 | .periph_buses = PL08X_AHB1, | |
| 31 | }, | |
| 32 | }; | |
| 33 | ||
| 8ba85f8b | 34 | static int pl08x_get_signal(const struct pl08x_channel_data *cd) |
| d807af47 | 35 | { |
| 8ba85f8b | 36 | return cd->min_signal; |
| d807af47 RS |
37 | } |
| 38 | ||
| 8ba85f8b | 39 | static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) |
| d807af47 RS |
40 | { |
| 41 | } | |
| 42 | ||
| f5c42271 | 43 | static struct pl08x_platform_data pl08x_pd = { |
| 4166a56a LW |
44 | /* Some reasonable memcpy defaults */ |
| 45 | .memcpy_burst_size = PL08X_BURST_SZ_256, | |
| 46 | .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS, | |
| d807af47 RS |
47 | .slave_channels = &pl08x_slave_channels[0], |
| 48 | .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels), | |
| d7cabeed MB |
49 | .get_xfer_signal = pl08x_get_signal, |
| 50 | .put_xfer_signal = pl08x_put_signal, | |
| d807af47 RS |
51 | .lli_buses = PL08X_AHB1, |
| 52 | .mem_buses = PL08X_AHB1, | |
| 19d95e1a KW |
53 | }; |
| 54 | ||
| 5b941238 RS |
55 | static struct lpc32xx_slc_platform_data lpc32xx_slc_data = { |
| 56 | .dma_filter = pl08x_filter_id, | |
| 57 | }; | |
| 58 | ||
| 59 | static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = { | |
| 60 | .dma_filter = pl08x_filter_id, | |
| 61 | }; | |
| 62 | ||
| 71d42e9c | 63 | static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { |
| f5c42271 | 64 | OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), |
| 5b941238 RS |
65 | OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash", |
| 66 | &lpc32xx_slc_data), | |
| 67 | OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash", | |
| 68 | &lpc32xx_mlc_data), | |
| f5c42271 | 69 | { } |
| 19d95e1a KW |
70 | }; |
| 71 | ||
| f5c42271 | 72 | static void __init lpc3250_machine_init(void) |
| 19d95e1a | 73 | { |
| 19d95e1a KW |
74 | lpc32xx_serial_init(); |
| 75 | ||
| 435ebcbc | 76 | of_platform_default_populate(NULL, lpc32xx_auxdata_lookup, NULL); |
| 19d95e1a KW |
77 | } |
| 78 | ||
| 19c233b7 | 79 | static const char *const lpc32xx_dt_compat[] __initconst = { |
| f5c42271 RS |
80 | "nxp,lpc3220", |
| 81 | "nxp,lpc3230", | |
| 82 | "nxp,lpc3240", | |
| 83 | "nxp,lpc3250", | |
| 84 | NULL | |
| 85 | }; | |
| 86 | ||
| 87 | DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)") | |
| bdec5ddd | 88 | .atag_offset = 0x100, |
| 19d95e1a | 89 | .map_io = lpc32xx_map_io, |
| f5c42271 RS |
90 | .init_machine = lpc3250_machine_init, |
| 91 | .dt_compat = lpc32xx_dt_compat, | |
| 19d95e1a | 92 | MACHINE_END |