[linux-2.6-block.git] / arch / arm / mach-loki / addr-map.c

/*
 * arch/arm/mach-loki/addr-map.c
 *
 * Address map functions for Marvell Loki (88RC8480) SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include "common.h"

/*
 * Generic Address Decode Windows bit settings
 */
#define TARGET_DDR		0
#define TARGET_DEV_BUS		1
#define TARGET_PCIE0		3
#define TARGET_PCIE1		4
#define ATTR_DEV_BOOT		0x0f
#define ATTR_DEV_CS2		0x1b
#define ATTR_DEV_CS1		0x1d
#define ATTR_DEV_CS0		0x1e
#define ATTR_PCIE_IO		0x51
#define ATTR_PCIE_MEM		0x59

/*
 * Helpers to get DDR bank info
 */
#define DDR_SIZE_CS(n)		DDR_REG(0x1500 + ((n) << 3))
#define DDR_BASE_CS(n)		DDR_REG(0x1504 + ((n) << 3))

/*
 * CPU Address Decode Windows registers
 */
#define CPU_WIN_CTRL(n)		BRIDGE_REG(0x000 | ((n) << 4))
#define CPU_WIN_BASE(n)		BRIDGE_REG(0x004 | ((n) << 4))
#define CPU_WIN_REMAP_LO(n)	BRIDGE_REG(0x008 | ((n) << 4))
#define CPU_WIN_REMAP_HI(n)	BRIDGE_REG(0x00c | ((n) << 4))


struct mbus_dram_target_info loki_mbus_dram_info;

static void __init setup_cpu_win(int win, u32 base, u32 size,
				 u8 target, u8 attr, int remap)
{
	u32 ctrl;

	base &= 0xffff0000;
	ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;

	writel(base, CPU_WIN_BASE(win));
	writel(ctrl, CPU_WIN_CTRL(win));
	if (win < 2) {
		if (remap < 0)
			remap = base;

		writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
		writel(0, CPU_WIN_REMAP_HI(win));
	}
}

void __init loki_setup_cpu_mbus(void)
{
	int i;
	int cs;

	/*
	 * First, disable and clear windows.
	 */
	for (i = 0; i < 8; i++) {
		writel(0, CPU_WIN_BASE(i));
		writel(0, CPU_WIN_CTRL(i));
		if (i < 2) {
			writel(0, CPU_WIN_REMAP_LO(i));
			writel(0, CPU_WIN_REMAP_HI(i));
		}
	}

	/*
	 * Setup windows for PCIe IO+MEM space.
	 */
	setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
		      TARGET_PCIE0, ATTR_PCIE_MEM, -1);
	setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
		      TARGET_PCIE1, ATTR_PCIE_MEM, -1);

	/*
	 * Setup MBUS dram target info.
	 */
	loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;

	for (i = 0, cs = 0; i < 4; i++) {
		u32 base = readl(DDR_BASE_CS(i));
		u32 size = readl(DDR_SIZE_CS(i));

		/*
		 * Chip select enabled?
		 */
		if (size & 1) {
			struct mbus_dram_window *w;

			w = &loki_mbus_dram_info.cs[cs++];
			w->cs_index = i;
			w->mbus_attr = 0xf & ~(1 << i);
			w->base = base & 0xffff0000;
			w->size = (size | 0x0000ffff) + 1;
		}
	}
	loki_mbus_dram_info.num_cs = cs;
}

void __init loki_setup_dev_boot_win(u32 base, u32 size)
{
	setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
}
Commit	Line	Data
777f9beb LB	1	/*
	2	* arch/arm/mach-loki/addr-map.c
	3	*
	4	* Address map functions for Marvell Loki (88RC8480) SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/mbus.h>
fced80c7	14	#include <linux/io.h>
a09e64fb	15	#include <mach/hardware.h>
777f9beb LB	16	#include "common.h"
	17
	18	/*
	19	* Generic Address Decode Windows bit settings
	20	*/
	21	#define TARGET_DDR 0
	22	#define TARGET_DEV_BUS 1
	23	#define TARGET_PCIE0 3
	24	#define TARGET_PCIE1 4
	25	#define ATTR_DEV_BOOT 0x0f
	26	#define ATTR_DEV_CS2 0x1b
	27	#define ATTR_DEV_CS1 0x1d
	28	#define ATTR_DEV_CS0 0x1e
	29	#define ATTR_PCIE_IO 0x51
	30	#define ATTR_PCIE_MEM 0x59
	31
	32	/*
	33	* Helpers to get DDR bank info
	34	*/
	35	#define DDR_SIZE_CS(n) DDR_REG(0x1500 + ((n) << 3))
	36	#define DDR_BASE_CS(n) DDR_REG(0x1504 + ((n) << 3))
	37
	38	/*
	39	* CPU Address Decode Windows registers
	40	*/
	41	#define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 \| ((n) << 4))
	42	#define CPU_WIN_BASE(n) BRIDGE_REG(0x004 \| ((n) << 4))
	43	#define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 \| ((n) << 4))
	44	#define CPU_WIN_REMAP_HI(n) BRIDGE_REG(0x00c \| ((n) << 4))
	45
	46
	47	struct mbus_dram_target_info loki_mbus_dram_info;
	48
	49	static void __init setup_cpu_win(int win, u32 base, u32 size,
	50	u8 target, u8 attr, int remap)
	51	{
	52	u32 ctrl;
	53
	54	base &= 0xffff0000;
	55	ctrl = ((size - 1) & 0xffff0000) \| (attr << 8) \| (1 << 5) \| target;
	56
	57	writel(base, CPU_WIN_BASE(win));
	58	writel(ctrl, CPU_WIN_CTRL(win));
	59	if (win < 2) {
	60	if (remap < 0)
	61	remap = base;
	62
	63	writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
	64	writel(0, CPU_WIN_REMAP_HI(win));
	65	}
	66	}
	67
	68	void __init loki_setup_cpu_mbus(void)
	69	{
	70	int i;
	71	int cs;
	72
	73	/*
	74	* First, disable and clear windows.
	75	*/
	76	for (i = 0; i < 8; i++) {
	77	writel(0, CPU_WIN_BASE(i));
	78	writel(0, CPU_WIN_CTRL(i));
	79	if (i < 2) {
80	writel(0, CPU_WIN_REMAP_LO(i));
81	writel(0, CPU_WIN_REMAP_HI(i));
82	}
83	}
84
85	/*
86	* Setup windows for PCIe IO+MEM space.
87	*/
88	setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
89	TARGET_PCIE0, ATTR_PCIE_MEM, -1);
90	setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
91	TARGET_PCIE1, ATTR_PCIE_MEM, -1);
92
93	/*
94	* Setup MBUS dram target info.
95	*/
96	loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
97
98	for (i = 0, cs = 0; i < 4; i++) {
99	u32 base = readl(DDR_BASE_CS(i));
100	u32 size = readl(DDR_SIZE_CS(i));
101
102	/*
103	* Chip select enabled?
104	*/
105	if (size & 1) {
106	struct mbus_dram_window *w;
107
108	w = &loki_mbus_dram_info.cs[cs++];
109	w->cs_index = i;
110	w->mbus_attr = 0xf & ~(1 << i);
111	w->base = base & 0xffff0000;
112	w->size = (size \| 0x0000ffff) + 1;
113	}
114	}
115	loki_mbus_dram_info.num_cs = cs;
116	}
117
118	void __init loki_setup_dev_boot_win(u32 base, u32 size)
119	{
120	setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
121	}