Commit | Line | Data |
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2295196c | 1 | /* lcd-panel.h |
2295196c MS |
2 | |
3 | written by Marc Singer | |
4 | 18 Jul 2005 | |
5 | ||
6 | Copyright (C) 2005 Marc Singer | |
7 | ||
8 | ----------- | |
9 | DESCRIPTION | |
10 | ----------- | |
11 | ||
12 | Only one panel may be defined at a time. | |
13 | ||
14 | The pixel clock is calculated to be no greater than the target. | |
15 | ||
16 | Each timing value is accompanied by a specification comment. | |
17 | ||
18 | UNITS/MIN/TYP/MAX | |
19 | ||
20 | Most of the units will be in clocks. | |
21 | ||
22 | USE_RGB555 | |
23 | ||
24 | Define this macro to configure the AMBA LCD controller to use an | |
25 | RGB555 encoding for the pels instead of the normal RGB565. | |
26 | ||
27 | LPD9520, LPD79524, LPD7A400, LPD7A404-10, LPD7A404-11 | |
28 | ||
29 | These boards are best approximated by 555 for all panels. Some | |
30 | can use an extra low-order bit of blue in bit 16 of the color | |
31 | value, but we don't have a way to communicate this non-linear | |
32 | mapping to the kernel. | |
33 | ||
34 | */ | |
35 | ||
36 | #if !defined (__LCD_PANEL_H__) | |
37 | # define __LCD_PANEL_H__ | |
38 | ||
39 | #if defined (MACH_LPD79520)\ | |
40 | || defined (MACH_LPD79524)\ | |
41 | || defined (MACH_LPD7A400)\ | |
42 | || defined (MACH_LPD7A404) | |
43 | # define USE_RGB555 | |
44 | #endif | |
45 | ||
46 | struct clcd_panel_extra { | |
47 | unsigned int hrmode; | |
48 | unsigned int clsen; | |
49 | unsigned int spsen; | |
50 | unsigned int pcdel; | |
51 | unsigned int revdel; | |
52 | unsigned int lpdel; | |
53 | unsigned int spldel; | |
54 | unsigned int pc2del; | |
55 | }; | |
56 | ||
57 | #define NS_TO_CLOCK(ns,c) ((((ns)*((c)/1000) + (1000000 - 1))/1000000)) | |
58 | #define CLOCK_TO_DIV(e,c) (((c) + (e) - 1)/(e)) | |
59 | ||
60 | #if defined CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT | |
61 | ||
62 | /* Logic Product Development LCD 3.5" QVGA HRTFT -10 */ | |
63 | /* Sharp PN LQ035Q7DB02 w/HRTFT controller chip */ | |
64 | ||
65 | #define PIX_CLOCK_TARGET (6800000) | |
66 | #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) | |
67 | #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) | |
68 | ||
69 | static struct clcd_panel lcd_panel = { | |
70 | .mode = { | |
71 | .name = "3.5in QVGA (LQ035Q7DB02)", | |
72 | .xres = 240, | |
73 | .yres = 320, | |
74 | .pixclock = PIX_CLOCK, | |
75 | .left_margin = 16, | |
76 | .right_margin = 21, | |
77 | .upper_margin = 8, // line/8/8/8 | |
78 | .lower_margin = 5, | |
79 | .hsync_len = 61, | |
80 | .vsync_len = NS_TO_CLOCK (60, PIX_CLOCK), | |
81 | .vmode = FB_VMODE_NONINTERLACED, | |
82 | }, | |
83 | .width = -1, | |
84 | .height = -1, | |
85 | .tim2 = TIM2_IPC | (PIX_CLOCK_DIVIDER - 2), | |
86 | .cntl = CNTL_LCDTFT | CNTL_WATERMARK, | |
87 | .bpp = 16, | |
88 | }; | |
89 | ||
90 | #define HAS_LCD_PANEL_EXTRA | |
91 | ||
92 | static struct clcd_panel_extra lcd_panel_extra = { | |
93 | .hrmode = 1, | |
94 | .clsen = 1, | |
95 | .spsen = 1, | |
96 | .pcdel = 8, | |
97 | .revdel = 7, | |
98 | .lpdel = 13, | |
99 | .spldel = 77, | |
100 | .pc2del = 208, | |
101 | }; | |
102 | ||
103 | #endif | |
104 | ||
105 | #if defined CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02 | |
106 | ||
107 | /* Logic Product Development LCD 5.7" QVGA -10 */ | |
108 | /* Sharp PN LQ057Q3DC02 */ | |
109 | /* QVGA mode, V/Q=LOW */ | |
110 | ||
111 | /* From Sharp on 2006.1.3. I believe some of the values are incorrect | |
112 | * based on the datasheet. | |
113 | ||
114 | Timing0 TIMING1 TIMING2 CONTROL | |
115 | 0x140A0C4C 0x080504EF 0x013F380D 0x00000829 | |
116 | HBP= 20 VBP= 8 BCD= 0 | |
117 | HFP= 10 VFP= 5 CPL=319 | |
118 | HSW= 12 VSW= 1 IOE= 0 | |
119 | PPL= 19 LPP=239 IPC= 1 | |
120 | IHS= 1 | |
121 | IVS= 1 | |
122 | ACB= 0 | |
123 | CSEL= 0 | |
124 | PCD= 13 | |
125 | ||
126 | */ | |
127 | ||
6cbdc8c5 | 128 | /* The full horizontal cycle (Th) is clock/360/400/450. */ |
2295196c MS |
129 | /* The full vertical cycle (Tv) is line/251/262/280. */ |
130 | ||
131 | #define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */ | |
132 | #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) | |
133 | #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) | |
134 | ||
135 | static struct clcd_panel lcd_panel = { | |
136 | .mode = { | |
137 | .name = "5.7in QVGA (LQ057Q3DC02)", | |
138 | .xres = 320, | |
139 | .yres = 240, | |
140 | .pixclock = PIX_CLOCK, | |
141 | .left_margin = 11, | |
142 | .right_margin = 400-11-320-2, | |
143 | .upper_margin = 7, // line/7/7/7 | |
144 | .lower_margin = 262-7-240-2, | |
145 | .hsync_len = 2, // clk/2/96/200 | |
146 | .vsync_len = 2, // line/2/-/34 | |
147 | .vmode = FB_VMODE_NONINTERLACED, | |
148 | }, | |
149 | .width = -1, | |
150 | .height = -1, | |
151 | .tim2 = TIM2_IHS | TIM2_IVS | |
152 | | (PIX_CLOCK_DIVIDER - 2), | |
153 | .cntl = CNTL_LCDTFT | CNTL_WATERMARK, | |
154 | .bpp = 16, | |
155 | }; | |
156 | ||
157 | #endif | |
158 | ||
159 | #if defined CONFIG_FB_ARMCLCD_SHARP_LQ64D343 | |
160 | ||
161 | /* Logic Product Development LCD 6.4" VGA -10 */ | |
162 | /* Sharp PN LQ64D343 */ | |
163 | ||
6cbdc8c5 | 164 | /* The full horizontal cycle (Th) is clock/750/800/900. */ |
2295196c MS |
165 | /* The full vertical cycle (Tv) is line/515/525/560. */ |
166 | ||
167 | #define PIX_CLOCK_TARGET (28330000) | |
168 | #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) | |
169 | #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) | |
170 | ||
171 | static struct clcd_panel lcd_panel = { | |
172 | .mode = { | |
173 | .name = "6.4in QVGA (LQ64D343)", | |
174 | .xres = 640, | |
175 | .yres = 480, | |
176 | .pixclock = PIX_CLOCK, | |
177 | .left_margin = 32, | |
178 | .right_margin = 800-32-640-96, | |
179 | .upper_margin = 32, // line/34/34/34 | |
180 | .lower_margin = 540-32-480-2, | |
181 | .hsync_len = 96, // clk/2/96/200 | |
182 | .vsync_len = 2, // line/2/-/34 | |
183 | .vmode = FB_VMODE_NONINTERLACED, | |
184 | }, | |
185 | .width = -1, | |
186 | .height = -1, | |
187 | .tim2 = TIM2_IHS | TIM2_IVS | |
188 | | (PIX_CLOCK_DIVIDER - 2), | |
189 | .cntl = CNTL_LCDTFT | CNTL_WATERMARK, | |
190 | .bpp = 16, | |
191 | }; | |
192 | ||
193 | #endif | |
194 | ||
195 | #if defined CONFIG_FB_ARMCLCD_SHARP_LQ10D368 | |
196 | ||
197 | /* Logic Product Development LCD 10.4" VGA -10 */ | |
198 | /* Sharp PN LQ10D368 */ | |
199 | ||
200 | #define PIX_CLOCK_TARGET (28330000) | |
201 | #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) | |
202 | #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) | |
203 | ||
204 | static struct clcd_panel lcd_panel = { | |
205 | .mode = { | |
206 | .name = "10.4in VGA (LQ10D368)", | |
207 | .xres = 640, | |
208 | .yres = 480, | |
209 | .pixclock = PIX_CLOCK, | |
210 | .left_margin = 21, | |
211 | .right_margin = 15, | |
212 | .upper_margin = 34, | |
213 | .lower_margin = 5, | |
214 | .hsync_len = 96, | |
215 | .vsync_len = 16, | |
216 | .vmode = FB_VMODE_NONINTERLACED, | |
217 | }, | |
218 | .width = -1, | |
219 | .height = -1, | |
220 | .tim2 = TIM2_IHS | TIM2_IVS | |
221 | | (PIX_CLOCK_DIVIDER - 2), | |
222 | .cntl = CNTL_LCDTFT | CNTL_WATERMARK, | |
223 | .bpp = 16, | |
224 | }; | |
225 | ||
226 | #endif | |
227 | ||
228 | #if defined CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41 | |
229 | ||
230 | /* Logic Product Development LCD 12.1" SVGA -10 */ | |
231 | /* Sharp PN LQ121S1DG41, was LQ121S1DG31 */ | |
232 | ||
233 | /* Note that with a 99993900 Hz HCLK, it is not possible to hit the | |
234 | * target clock frequency range of 35MHz to 42MHz. */ | |
235 | ||
236 | /* If the target pixel clock is substantially lower than the panel | |
237 | * spec, this is done to prevent the LCD display from glitching when | |
238 | * the CPU is under load. A pixel clock higher than 25MHz | |
239 | * (empirically determined) will compete with the CPU for bus cycles | |
240 | * for the Ethernet chip. However, even a pixel clock of 10MHz | |
241 | * competes with Compact Flash interface during some operations | |
242 | * (fdisk, e2fsck). And, at that speed the display may have a visible | |
243 | * flicker. */ | |
244 | ||
6cbdc8c5 | 245 | /* The full horizontal cycle (Th) is clock/832/1056/1395. */ |
2295196c MS |
246 | |
247 | #define PIX_CLOCK_TARGET (20000000) | |
248 | #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) | |
249 | #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) | |
250 | ||
251 | static struct clcd_panel lcd_panel = { | |
252 | .mode = { | |
253 | .name = "12.1in SVGA (LQ121S1DG41)", | |
254 | .xres = 800, | |
255 | .yres = 600, | |
256 | .pixclock = PIX_CLOCK, | |
257 | .left_margin = 89, // ns/5/-/(1/PIX_CLOCK)-10 | |
258 | .right_margin = 1056-800-89-128, | |
259 | .upper_margin = 23, // line/23/23/23 | |
260 | .lower_margin = 44, | |
261 | .hsync_len = 128, // clk/2/128/200 | |
262 | .vsync_len = 4, // line/2/4/6 | |
263 | .vmode = FB_VMODE_NONINTERLACED, | |
264 | }, | |
265 | .width = -1, | |
266 | .height = -1, | |
267 | .tim2 = TIM2_IHS | TIM2_IVS | |
268 | | (PIX_CLOCK_DIVIDER - 2), | |
269 | .cntl = CNTL_LCDTFT | CNTL_WATERMARK, | |
270 | .bpp = 16, | |
271 | }; | |
272 | ||
273 | #endif | |
274 | ||
275 | #if defined CONFIG_FB_ARMCLCD_HITACHI | |
276 | ||
277 | /* Hitachi*/ | |
278 | /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */ | |
279 | ||
280 | #define PIX_CLOCK_TARGET (49000000) | |
281 | #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) | |
282 | #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) | |
283 | ||
284 | static struct clcd_panel lcd_panel = { | |
285 | .mode = { | |
286 | .name = "Hitachi 800x480", | |
287 | .xres = 800, | |
288 | .yres = 480, | |
289 | .pixclock = PIX_CLOCK, | |
290 | .left_margin = 88, | |
291 | .right_margin = 40, | |
292 | .upper_margin = 32, | |
293 | .lower_margin = 11, | |
294 | .hsync_len = 128, | |
295 | .vsync_len = 2, | |
296 | .vmode = FB_VMODE_NONINTERLACED, | |
297 | }, | |
298 | .width = -1, | |
299 | .height = -1, | |
300 | .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS | |
301 | | (PIX_CLOCK_DIVIDER - 2), | |
302 | .cntl = CNTL_LCDTFT | CNTL_WATERMARK, | |
303 | .bpp = 16, | |
304 | }; | |
305 | ||
306 | #endif | |
307 | ||
308 | ||
309 | #if defined CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE | |
310 | ||
311 | /* AU Optotronics A070VW01 7.0 Wide Screen color Display*/ | |
312 | /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */ | |
313 | ||
314 | #define PIX_CLOCK_TARGET (10000000) | |
315 | #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) | |
316 | #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) | |
317 | ||
318 | static struct clcd_panel lcd_panel = { | |
319 | .mode = { | |
320 | .name = "7.0in Wide (A070VW01)", | |
321 | .xres = 480, | |
322 | .yres = 234, | |
323 | .pixclock = PIX_CLOCK, | |
324 | .left_margin = 30, | |
325 | .right_margin = 25, | |
326 | .upper_margin = 14, | |
327 | .lower_margin = 12, | |
328 | .hsync_len = 100, | |
329 | .vsync_len = 1, | |
330 | .vmode = FB_VMODE_NONINTERLACED, | |
331 | }, | |
332 | .width = -1, | |
333 | .height = -1, | |
334 | .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS | |
335 | | (PIX_CLOCK_DIVIDER - 2), | |
336 | .cntl = CNTL_LCDTFT | CNTL_WATERMARK, | |
337 | .bpp = 16, | |
338 | }; | |
339 | ||
340 | #endif | |
341 | ||
342 | #undef NS_TO_CLOCK | |
343 | #undef CLOCK_TO_DIV | |
344 | ||
345 | #endif /* __LCD_PANEL_H__ */ |