projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 651c74c7 | 1 | /* |
| a09e64fb | 2 | * arch/arm/mach-kirkwood/include/mach/kirkwood.h |
| 651c74c7 SB |
3 | * |
| 4 | * Generic definitions for Marvell Kirkwood SoC flavors: | |
| 5 | * 88F6180, 88F6192 and 88F6281. | |
| 6 | * | |
| 7 | * This file is licensed under the terms of the GNU General Public | |
| 8 | * License version 2. This program is licensed "as is" without any | |
| 9 | * warranty of any kind, whether express or implied. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __ASM_ARCH_KIRKWOOD_H | |
| 13 | #define __ASM_ARCH_KIRKWOOD_H | |
| 14 | ||
| 15 | /* | |
| 16 | * Marvell Kirkwood address maps. | |
| 17 | * | |
| 18 | * phys | |
| 19 | * e0000000 PCIe Memory space | |
| 20 | * f1000000 on-chip peripheral registers | |
| 21 | * f2000000 PCIe I/O space | |
| 22 | * f3000000 NAND controller address window | |
| c1191b0e | 23 | * f4000000 Security Accelerator SRAM |
| 651c74c7 SB |
24 | * |
| 25 | * virt phys size | |
| 26 | * fee00000 f1000000 1M on-chip peripheral registers | |
| 27 | * fef00000 f2000000 1M PCIe I/O space | |
| 28 | */ | |
| 29 | ||
| c1191b0e NP |
30 | #define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000 |
| 31 | #define KIRKWOOD_SRAM_SIZE SZ_2K | |
| 32 | ||
| 651c74c7 | 33 | #define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 |
| fc63b723 | 34 | #define KIRKWOOD_NAND_MEM_SIZE SZ_1K |
| 651c74c7 SB |
35 | |
| 36 | #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 | |
| 37 | #define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 | |
| 38 | #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 | |
| 39 | #define KIRKWOOD_PCIE_IO_SIZE SZ_1M | |
| 40 | ||
| 41 | #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 | |
| 42 | #define KIRKWOOD_REGS_VIRT_BASE 0xfee00000 | |
| 43 | #define KIRKWOOD_REGS_SIZE SZ_1M | |
| 44 | ||
| 45 | #define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 | |
| 46 | #define KIRKWOOD_PCIE_MEM_SIZE SZ_128M | |
| 47 | ||
| 651c74c7 SB |
48 | /* |
| 49 | * Register Map | |
| 50 | */ | |
| 51 | #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) | |
| 52 | #define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) | |
| e50b6bef | 53 | #define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418) |
| 651c74c7 SB |
54 | |
| 55 | #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) | |
| 56 | #define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) | |
| 57 | #define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) | |
| 58 | #define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) | |
| 59 | #define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) | |
| 60 | #define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) | |
| 6574e001 | 61 | #define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) |
| 651c74c7 SB |
62 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) |
| 63 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | |
| 64 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | |
| 65 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) | |
| 66 | ||
| fdd8b079 NP |
67 | #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) |
| 68 | ||
| ae5c8c83 NP |
69 | #define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000) |
| 70 | ||
| 651c74c7 | 71 | #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) |
| e8b2b7ba RK |
72 | #define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) |
| 73 | #define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) | |
| 651c74c7 SB |
74 | |
| 75 | #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) | |
| 76 | ||
| 09c0ed2e SB |
77 | #define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60800) |
| 78 | #define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60800) | |
| 79 | #define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60900) | |
| 80 | #define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60900) | |
| 81 | #define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60A00) | |
| 82 | #define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60A00) | |
| 83 | #define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60B00) | |
| 84 | #define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60B00) | |
| 85 | ||
| 651c74c7 SB |
86 | #define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000) |
| 87 | #define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) | |
| 88 | ||
| 89 | #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) | |
| e8b2b7ba RK |
90 | #define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000) |
| 91 | #define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050) | |
| 92 | #define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330) | |
| 93 | #define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050) | |
| 94 | #define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330) | |
| 651c74c7 | 95 | |
| 8235ee00 NP |
96 | #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) |
| 97 | ||
| fdd8b079 NP |
98 | /* |
| 99 | * Supported devices and revisions. | |
| 100 | */ | |
| 101 | #define MV88F6281_DEV_ID 0x6281 | |
| 102 | #define MV88F6281_REV_Z0 0 | |
| 103 | #define MV88F6281_REV_A0 2 | |
| 104 | ||
| 105 | #define MV88F6192_DEV_ID 0x6192 | |
| 106 | #define MV88F6192_REV_Z0 0 | |
| 107 | #define MV88F6192_REV_A0 2 | |
| 108 | ||
| 109 | #define MV88F6180_DEV_ID 0x6180 | |
| 110 | #define MV88F6180_REV_A0 2 | |
| 651c74c7 | 111 | |
| 651c74c7 | 112 | #endif |