[linux-block.git] / arch / arm / mach-kirkwood / common.c

/*
 * arch/arm/mach-kirkwood/common.c
 *
 * Core functions for Marvell Kirkwood SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/ata_platform.h>
#include <linux/mtd/nand.h>
#include <linux/dma-mapping.h>
#include <linux/clk-provider.h>
#include <linux/spinlock.h>
#include <net/dsa.h>
#include <asm/page.h>
#include <asm/timex.h>
#include <asm/kexec.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/kirkwood.h>
#include <mach/bridge-regs.h>
#include <plat/audio.h>
#include <plat/cache-feroceon-l2.h>
#include <plat/mvsdio.h>
#include <plat/orion_nand.h>
#include <plat/ehci-orion.h>
#include <plat/common.h>
#include <plat/time.h>
#include <plat/addr-map.h>
#include <plat/mv_xor.h>
#include "common.h"

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc kirkwood_io_desc[] __initdata = {
	{
		.virtual	= KIRKWOOD_PCIE_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
		.length		= KIRKWOOD_PCIE_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= KIRKWOOD_PCIE1_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
		.length		= KIRKWOOD_PCIE1_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= KIRKWOOD_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
		.length		= KIRKWOOD_REGS_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init kirkwood_map_io(void)
{
	iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
}

/*
 * Default clock control bits.  Any bit _not_ set in this variable
 * will be cleared from the hardware after platform devices have been
 * registered.  Some reserved bits must be set to 1.
 */
unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;


/*****************************************************************************
 * CLK tree
 ****************************************************************************/
static DEFINE_SPINLOCK(gating_lock);
static struct clk *tclk;

static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
{
	return clk_register_gate(NULL, name, "tclk", CLK_IGNORE_UNUSED,
				 (void __iomem *)CLOCK_GATING_CTRL,
				 bit_idx, 0, &gating_lock);
}

void __init kirkwood_clk_init(void)
{
	struct clk *runit, *ge0, *ge1, *sata0, *sata1, *usb0, *sdio;

	tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
				       CLK_IS_ROOT, kirkwood_tclk);

	runit = kirkwood_register_gate("runit",  CGC_BIT_RUNIT);
	ge0 = kirkwood_register_gate("ge0",    CGC_BIT_GE0);
	ge1 = kirkwood_register_gate("ge1",    CGC_BIT_GE1);
	sata0 = kirkwood_register_gate("sata0",  CGC_BIT_SATA0);
	sata1 = kirkwood_register_gate("sata1",  CGC_BIT_SATA1);
	usb0 = kirkwood_register_gate("usb0",   CGC_BIT_USB0);
	sdio = kirkwood_register_gate("sdio",   CGC_BIT_SDIO);
	kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
	kirkwood_register_gate("xor0",   CGC_BIT_XOR0);
	kirkwood_register_gate("xor1",   CGC_BIT_XOR1);
	kirkwood_register_gate("pex0",   CGC_BIT_PEX0);
	kirkwood_register_gate("pex1",   CGC_BIT_PEX1);
	kirkwood_register_gate("audio",  CGC_BIT_AUDIO);
	kirkwood_register_gate("tdm",    CGC_BIT_TDM);
	kirkwood_register_gate("tsu",    CGC_BIT_TSU);

	/* clkdev entries, mapping clks to devices */
	orion_clkdev_add(NULL, "orion_spi.0", runit);
	orion_clkdev_add(NULL, "orion_spi.1", runit);
	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
	orion_clkdev_add(NULL, "orion_wdt", tclk);
	orion_clkdev_add("0", "sata_mv.0", sata0);
	orion_clkdev_add("1", "sata_mv.0", sata1);
	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
	orion_clkdev_add(NULL, "orion_nand", runit);
	orion_clkdev_add(NULL, "mvsdio", sdio);
}

/*****************************************************************************
 * EHCI0
 ****************************************************************************/
void __init kirkwood_ehci_init(void)
{
	kirkwood_clk_ctrl |= CGC_USB0;
	orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
}


/*****************************************************************************
 * GE00
 ****************************************************************************/
void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	kirkwood_clk_ctrl |= CGC_GE0;

	orion_ge00_init(eth_data,
			GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
			IRQ_KIRKWOOD_GE00_ERR);
}


/*****************************************************************************
 * GE01
 ****************************************************************************/
void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
{

	kirkwood_clk_ctrl |= CGC_GE1;

	orion_ge01_init(eth_data,
			GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
			IRQ_KIRKWOOD_GE01_ERR);
}


/*****************************************************************************
 * Ethernet switch
 ****************************************************************************/
void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
{
	orion_ge00_switch_init(d, irq);
}


/*****************************************************************************
 * NAND flash
 ****************************************************************************/
static struct resource kirkwood_nand_resource = {
	.flags		= IORESOURCE_MEM,
	.start		= KIRKWOOD_NAND_MEM_PHYS_BASE,
	.end		= KIRKWOOD_NAND_MEM_PHYS_BASE +
				KIRKWOOD_NAND_MEM_SIZE - 1,
};

static struct orion_nand_data kirkwood_nand_data = {
	.cle		= 0,
	.ale		= 1,
	.width		= 8,
};

static struct platform_device kirkwood_nand_flash = {
	.name		= "orion_nand",
	.id		= -1,
	.dev		= {
		.platform_data	= &kirkwood_nand_data,
	},
	.resource	= &kirkwood_nand_resource,
	.num_resources	= 1,
};

void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
			       int chip_delay)
{
	kirkwood_clk_ctrl |= CGC_RUNIT;
	kirkwood_nand_data.parts = parts;
	kirkwood_nand_data.nr_parts = nr_parts;
	kirkwood_nand_data.chip_delay = chip_delay;
	platform_device_register(&kirkwood_nand_flash);
}

void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
				   int (*dev_ready)(struct mtd_info *))
{
	kirkwood_clk_ctrl |= CGC_RUNIT;
	kirkwood_nand_data.parts = parts;
	kirkwood_nand_data.nr_parts = nr_parts;
	kirkwood_nand_data.dev_ready = dev_ready;
	platform_device_register(&kirkwood_nand_flash);
}

/*****************************************************************************
 * SoC RTC
 ****************************************************************************/
static void __init kirkwood_rtc_init(void)
{
	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
}


/*****************************************************************************
 * SATA
 ****************************************************************************/
void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
{
	kirkwood_clk_ctrl |= CGC_SATA0;
	if (sata_data->n_ports > 1)
		kirkwood_clk_ctrl |= CGC_SATA1;

	orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
}


/*****************************************************************************
 * SD/SDIO/MMC
 ****************************************************************************/
static struct resource mvsdio_resources[] = {
	[0] = {
		.start	= SDIO_PHYS_BASE,
		.end	= SDIO_PHYS_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_KIRKWOOD_SDIO,
		.end	= IRQ_KIRKWOOD_SDIO,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 mvsdio_dmamask = DMA_BIT_MASK(32);

static struct platform_device kirkwood_sdio = {
	.name		= "mvsdio",
	.id		= -1,
	.dev		= {
		.dma_mask = &mvsdio_dmamask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.num_resources	= ARRAY_SIZE(mvsdio_resources),
	.resource	= mvsdio_resources,
};

void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
{
	u32 dev, rev;

	kirkwood_pcie_id(&dev, &rev);
	if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
		mvsdio_data->clock = 100000000;
	else
		mvsdio_data->clock = 200000000;
	kirkwood_clk_ctrl |= CGC_SDIO;
	kirkwood_sdio.dev.platform_data = mvsdio_data;
	platform_device_register(&kirkwood_sdio);
}


/*****************************************************************************
 * SPI
 ****************************************************************************/
void __init kirkwood_spi_init()
{
	kirkwood_clk_ctrl |= CGC_RUNIT;
	orion_spi_init(SPI_PHYS_BASE);
}


/*****************************************************************************
 * I2C
 ****************************************************************************/
void __init kirkwood_i2c_init(void)
{
	orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
}


/*****************************************************************************
 * UART0
 ****************************************************************************/

void __init kirkwood_uart0_init(void)
{
	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
			 IRQ_KIRKWOOD_UART_0, tclk);
}


/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init kirkwood_uart1_init(void)
{
	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
			 IRQ_KIRKWOOD_UART_1, tclk);
}

/*****************************************************************************
 * Cryptographic Engines and Security Accelerator (CESA)
 ****************************************************************************/
void __init kirkwood_crypto_init(void)
{
	kirkwood_clk_ctrl |= CGC_CRYPTO;
	orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
			  KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
}


/*****************************************************************************
 * XOR0
 ****************************************************************************/
void __init kirkwood_xor0_init(void)
{
	kirkwood_clk_ctrl |= CGC_XOR0;

	orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
			IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
}


/*****************************************************************************
 * XOR1
 ****************************************************************************/
void __init kirkwood_xor1_init(void)
{
	kirkwood_clk_ctrl |= CGC_XOR1;

	orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
			IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
}


/*****************************************************************************
 * Watchdog
 ****************************************************************************/
void __init kirkwood_wdt_init(void)
{
	orion_wdt_init();
}


/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init kirkwood_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
}

int kirkwood_tclk;

static int __init kirkwood_find_tclk(void)
{
	u32 dev, rev;

	kirkwood_pcie_id(&dev, &rev);

	if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
		if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
			return 200000000;

	return 166666667;
}

static void __init kirkwood_timer_init(void)
{
	kirkwood_tclk = kirkwood_find_tclk();

	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
}

struct sys_timer kirkwood_timer = {
	.init = kirkwood_timer_init,
};

/*****************************************************************************
 * Audio
 ****************************************************************************/
static struct resource kirkwood_i2s_resources[] = {
	[0] = {
		.start  = AUDIO_PHYS_BASE,
		.end    = AUDIO_PHYS_BASE + SZ_16K - 1,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = IRQ_KIRKWOOD_I2S,
		.end    = IRQ_KIRKWOOD_I2S,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
	.burst       = 128,
};

static struct platform_device kirkwood_i2s_device = {
	.name		= "kirkwood-i2s",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(kirkwood_i2s_resources),
	.resource	= kirkwood_i2s_resources,
	.dev		= {
		.platform_data	= &kirkwood_i2s_data,
	},
};

static struct platform_device kirkwood_pcm_device = {
	.name		= "kirkwood-pcm-audio",
	.id		= -1,
};

void __init kirkwood_audio_init(void)
{
	kirkwood_clk_ctrl |= CGC_AUDIO;
	platform_device_register(&kirkwood_i2s_device);
	platform_device_register(&kirkwood_pcm_device);
}

/*****************************************************************************
 * General
 ****************************************************************************/
/*
 * Identify device ID and revision.
 */
char * __init kirkwood_id(void)
{
	u32 dev, rev;

	kirkwood_pcie_id(&dev, &rev);

	if (dev == MV88F6281_DEV_ID) {
		if (rev == MV88F6281_REV_Z0)
			return "MV88F6281-Z0";
		else if (rev == MV88F6281_REV_A0)
			return "MV88F6281-A0";
		else if (rev == MV88F6281_REV_A1)
			return "MV88F6281-A1";
		else
			return "MV88F6281-Rev-Unsupported";
	} else if (dev == MV88F6192_DEV_ID) {
		if (rev == MV88F6192_REV_Z0)
			return "MV88F6192-Z0";
		else if (rev == MV88F6192_REV_A0)
			return "MV88F6192-A0";
		else if (rev == MV88F6192_REV_A1)
			return "MV88F6192-A1";
		else
			return "MV88F6192-Rev-Unsupported";
	} else if (dev == MV88F6180_DEV_ID) {
		if (rev == MV88F6180_REV_A0)
			return "MV88F6180-Rev-A0";
		else if (rev == MV88F6180_REV_A1)
			return "MV88F6180-Rev-A1";
		else
			return "MV88F6180-Rev-Unsupported";
	} else if (dev == MV88F6282_DEV_ID) {
		if (rev == MV88F6282_REV_A0)
			return "MV88F6282-Rev-A0";
		else if (rev == MV88F6282_REV_A1)
			return "MV88F6282-Rev-A1";
		else
			return "MV88F6282-Rev-Unsupported";
	} else {
		return "Device-Unknown";
	}
}

void __init kirkwood_l2_init(void)
{
#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
	writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
	feroceon_l2_init(1);
#else
	writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
	feroceon_l2_init(0);
#endif
}

void __init kirkwood_init(void)
{
	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
		kirkwood_id(), kirkwood_tclk);

	/*
	 * Disable propagation of mbus errors to the CPU local bus,
	 * as this causes mbus errors (which can occur for example
	 * for PCI aborts) to throw CPU aborts, which we're not set
	 * up to deal with.
	 */
	writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);

	kirkwood_setup_cpu_mbus();

#ifdef CONFIG_CACHE_FEROCEON_L2
	kirkwood_l2_init();
#endif

	/* Setup root of clk tree */
	kirkwood_clk_init();

	/* internal devices that every board has */
	kirkwood_rtc_init();
	kirkwood_wdt_init();
	kirkwood_xor0_init();
	kirkwood_xor1_init();
	kirkwood_crypto_init();

#ifdef CONFIG_KEXEC 
	kexec_reinit = kirkwood_enable_pcie;
#endif
}

static int __init kirkwood_clock_gate(void)
{
	unsigned int curr = readl(CLOCK_GATING_CTRL);
	u32 dev, rev;

	kirkwood_pcie_id(&dev, &rev);
	printk(KERN_DEBUG "Gating clock of unused units\n");
	printk(KERN_DEBUG "before: 0x%08x\n", curr);

	/* Make sure those units are accessible */
	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);

	/* For SATA: first shutdown the phy */
	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
		/* Disable PLL and IVREF */
		writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
		/* Disable PHY */
		writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
	}
	if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
		/* Disable PLL and IVREF */
		writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
		/* Disable PHY */
		writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
	}
	
	/* For PCIe: first shutdown the phy */
	if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
		writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
		while (1)
			if (readl(PCIE_STATUS) & 0x1)
				break;
		writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
	}

	/* For PCIe 1: first shutdown the phy */
	if (dev == MV88F6282_DEV_ID) {
		if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
			writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
			while (1)
				if (readl(PCIE1_STATUS) & 0x1)
					break;
			writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
		}
	} else  /* keep this bit set for devices that don't have PCIe1 */
		kirkwood_clk_ctrl |= CGC_PEX1;

	/* Now gate clock the required units */
	writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
	printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));

	return 0;
}
late_initcall(kirkwood_clock_gate);

void kirkwood_restart(char mode, const char *cmd)
{
	/*
	 * Enable soft reset to assert RSTOUTn.
	 */
	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);

	/*
	 * Assert soft reset.
	 */
	writel(SOFT_RESET, SYSTEM_SOFT_RESET);

	while (1)
		;
}
Commit	Line	Data
651c74c7 SB	1	/*
	2	* arch/arm/mach-kirkwood/common.c
	3	*
	4	* Core functions for Marvell Kirkwood SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/serial_8250.h>
651c74c7	15	#include <linux/ata_platform.h>
fb7b2d3f	16	#include <linux/mtd/nand.h>
ee962723	17	#include <linux/dma-mapping.h>
2f129bf4 AL	18	#include <linux/clk-provider.h>
2f129bf4 AL	19	#include <linux/spinlock.h>
dcf1cece	20	#include <net/dsa.h>
651c74c7 SB	21	#include <asm/page.h>
651c74c7 SB	22	#include <asm/timex.h>
9c15364f	23	#include <asm/kexec.h>
651c74c7 SB	24	#include <asm/mach/map.h>
651c74c7 SB	25	#include <asm/mach/time.h>
a09e64fb	26	#include <mach/kirkwood.h>
fdd8b079	27	#include <mach/bridge-regs.h>
49106c72	28	#include <plat/audio.h>
6f088f1d	29	#include <plat/cache-feroceon-l2.h>
8235ee00	30	#include <plat/mvsdio.h>
6f088f1d	31	#include <plat/orion_nand.h>
72053353	32	#include <plat/ehci-orion.h>
28a2b450	33	#include <plat/common.h>
6f088f1d	34	#include <plat/time.h>
45173d5e	35	#include <plat/addr-map.h>
2f129bf4	36	#include <plat/mv_xor.h>
651c74c7 SB	37	#include "common.h"
	38
	39	/*****************************************************************************
	40	* I/O Address Mapping
	41	****************************************************************************/
	42	static struct map_desc kirkwood_io_desc[] __initdata = {
	43	{
	44	.virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
	45	.pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
	46	.length = KIRKWOOD_PCIE_IO_SIZE,
	47	.type = MT_DEVICE,
ffd58bd2 SB	48	}, {
	49	.virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
	50	.pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
	51	.length = KIRKWOOD_PCIE1_IO_SIZE,
	52	.type = MT_DEVICE,
651c74c7 SB	53	}, {
	54	.virtual = KIRKWOOD_REGS_VIRT_BASE,
	55	.pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
	56	.length = KIRKWOOD_REGS_SIZE,
	57	.type = MT_DEVICE,
	58	},
	59	};
	60
	61	void __init kirkwood_map_io(void)
	62	{
	63	iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
	64	}
	65
e8b2b7ba RK	66	/*
	67	* Default clock control bits. Any bit _not_ set in this variable
	68	* will be cleared from the hardware after platform devices have been
	69	* registered. Some reserved bits must be set to 1.
	70	*/
	71	unsigned int kirkwood_clk_ctrl = CGC_DUNIT \| CGC_RESERVED;
7e3819d8	72
651c74c7	73
2f129bf4 AL	74	/*****************************************************************************
	75	* CLK tree
	76	****************************************************************************/
	77	static DEFINE_SPINLOCK(gating_lock);
	78	static struct clk *tclk;
	79
	80	static struct clk __init kirkwood_register_gate(const char name, u8 bit_idx)
	81	{
	82	return clk_register_gate(NULL, name, "tclk", CLK_IGNORE_UNUSED,
	83	(void __iomem *)CLOCK_GATING_CTRL,
	84	bit_idx, 0, &gating_lock);
	85	}
	86
	87	void __init kirkwood_clk_init(void)
	88	{
f4f7561e	89	struct clk runit, ge0, ge1, sata0, sata1, usb0, *sdio;
4574b886	90
2f129bf4 AL	91	tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
	92	CLK_IS_ROOT, kirkwood_tclk);
	93
4574b886	94	runit = kirkwood_register_gate("runit", CGC_BIT_RUNIT);
452503eb AL	95	ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0);
452503eb AL	96	ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1);
eee98990 AL	97	sata0 = kirkwood_register_gate("sata0", CGC_BIT_SATA0);
eee98990 AL	98	sata1 = kirkwood_register_gate("sata1", CGC_BIT_SATA1);
8c869eda	99	usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0);
f4f7561e	100	sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO);
2f129bf4 AL	101	kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
	102	kirkwood_register_gate("xor0", CGC_BIT_XOR0);
	103	kirkwood_register_gate("xor1", CGC_BIT_XOR1);
	104	kirkwood_register_gate("pex0", CGC_BIT_PEX0);
	105	kirkwood_register_gate("pex1", CGC_BIT_PEX1);
	106	kirkwood_register_gate("audio", CGC_BIT_AUDIO);
	107	kirkwood_register_gate("tdm", CGC_BIT_TDM);
	108	kirkwood_register_gate("tsu", CGC_BIT_TSU);
4574b886 AL	109
	110	/* clkdev entries, mapping clks to devices */
	111	orion_clkdev_add(NULL, "orion_spi.0", runit);
	112	orion_clkdev_add(NULL, "orion_spi.1", runit);
452503eb AL	113	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
452503eb AL	114	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
4f04be62	115	orion_clkdev_add(NULL, "orion_wdt", tclk);
eee98990 AL	116	orion_clkdev_add("0", "sata_mv.0", sata0);
eee98990 AL	117	orion_clkdev_add("1", "sata_mv.0", sata1);
8c869eda	118	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
9c2bd504	119	orion_clkdev_add(NULL, "orion_nand", runit);
f4f7561e	120	orion_clkdev_add(NULL, "mvsdio", sdio);
2f129bf4 AL	121	}
2f129bf4 AL	122
651c74c7 SB	123	/*****************************************************************************
	124	* EHCI0
	125	****************************************************************************/
651c74c7 SB	126	void __init kirkwood_ehci_init(void)
651c74c7 SB	127	{
e8b2b7ba	128	kirkwood_clk_ctrl \|= CGC_USB0;
72053353	129	orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
651c74c7 SB	130	}
	131
	132
	133	/*****************************************************************************
	134	* GE00
	135	****************************************************************************/
651c74c7 SB	136	void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
651c74c7 SB	137	{
e8b2b7ba	138	kirkwood_clk_ctrl \|= CGC_GE0;
651c74c7	139
db33f4de	140	orion_ge00_init(eth_data,
7e3819d8	141	GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
452503eb	142	IRQ_KIRKWOOD_GE00_ERR);
651c74c7 SB	143	}
	144
	145
d15fb9ef RS	146	/*****************************************************************************
	147	* GE01
	148	****************************************************************************/
d15fb9ef RS	149	void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
d15fb9ef RS	150	{
7e3819d8	151
e8b2b7ba	152	kirkwood_clk_ctrl \|= CGC_GE1;
d15fb9ef	153
db33f4de	154	orion_ge01_init(eth_data,
7e3819d8	155	GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
452503eb	156	IRQ_KIRKWOOD_GE01_ERR);
d15fb9ef RS	157	}
	158
	159
dcf1cece LB	160	/*****************************************************************************
	161	* Ethernet switch
	162	****************************************************************************/
dcf1cece LB	163	void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
dcf1cece LB	164	{
7e3819d8	165	orion_ge00_switch_init(d, irq);
dcf1cece LB	166	}
	167
	168
fb7b2d3f NP	169	/*****************************************************************************
	170	* NAND flash
	171	****************************************************************************/
	172	static struct resource kirkwood_nand_resource = {
	173	.flags = IORESOURCE_MEM,
	174	.start = KIRKWOOD_NAND_MEM_PHYS_BASE,
	175	.end = KIRKWOOD_NAND_MEM_PHYS_BASE +
	176	KIRKWOOD_NAND_MEM_SIZE - 1,
	177	};
	178
	179	static struct orion_nand_data kirkwood_nand_data = {
	180	.cle = 0,
	181	.ale = 1,
	182	.width = 8,
	183	};
	184
	185	static struct platform_device kirkwood_nand_flash = {
	186	.name = "orion_nand",
	187	.id = -1,
	188	.dev = {
	189	.platform_data = &kirkwood_nand_data,
	190	},
	191	.resource = &kirkwood_nand_resource,
	192	.num_resources = 1,
	193	};
	194
	195	void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
	196	int chip_delay)
	197	{
e8b2b7ba	198	kirkwood_clk_ctrl \|= CGC_RUNIT;
fb7b2d3f NP	199	kirkwood_nand_data.parts = parts;
	200	kirkwood_nand_data.nr_parts = nr_parts;
	201	kirkwood_nand_data.chip_delay = chip_delay;
	202	platform_device_register(&kirkwood_nand_flash);
	203	}
	204
010937ec BD	205	void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
	206	int (dev_ready)(struct mtd_info ))
	207	{
	208	kirkwood_clk_ctrl \|= CGC_RUNIT;
	209	kirkwood_nand_data.parts = parts;
	210	kirkwood_nand_data.nr_parts = nr_parts;
	211	kirkwood_nand_data.dev_ready = dev_ready;
	212	platform_device_register(&kirkwood_nand_flash);
	213	}
fb7b2d3f	214
651c74c7 SB	215	/*****************************************************************************
	216	* SoC RTC
	217	****************************************************************************/
e871b87a	218	static void __init kirkwood_rtc_init(void)
651c74c7	219	{
4748058c	220	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
651c74c7 SB	221	}
	222
	223
	224	/*****************************************************************************
	225	* SATA
	226	****************************************************************************/
651c74c7 SB	227	void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
651c74c7 SB	228	{
e8b2b7ba RK	229	kirkwood_clk_ctrl \|= CGC_SATA0;
	230	if (sata_data->n_ports > 1)
	231	kirkwood_clk_ctrl \|= CGC_SATA1;
9e613f8a	232
db33f4de	233	orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
651c74c7 SB	234	}
	235
	236
8235ee00 NP	237	/*****************************************************************************
	238	* SD/SDIO/MMC
	239	****************************************************************************/
	240	static struct resource mvsdio_resources[] = {
	241	[0] = {
	242	.start = SDIO_PHYS_BASE,
	243	.end = SDIO_PHYS_BASE + SZ_1K - 1,
	244	.flags = IORESOURCE_MEM,
	245	},
	246	[1] = {
	247	.start = IRQ_KIRKWOOD_SDIO,
	248	.end = IRQ_KIRKWOOD_SDIO,
	249	.flags = IORESOURCE_IRQ,
	250	},
	251	};
	252
5c602551	253	static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
8235ee00 NP	254
	255	static struct platform_device kirkwood_sdio = {
	256	.name = "mvsdio",
	257	.id = -1,
	258	.dev = {
	259	.dma_mask = &mvsdio_dmamask,
5c602551	260	.coherent_dma_mask = DMA_BIT_MASK(32),
8235ee00 NP	261	},
	262	.num_resources = ARRAY_SIZE(mvsdio_resources),
	263	.resource = mvsdio_resources,
	264	};
	265
	266	void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
	267	{
	268	u32 dev, rev;
	269
	270	kirkwood_pcie_id(&dev, &rev);
1e4d2d3d	271	if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
8235ee00 NP	272	mvsdio_data->clock = 100000000;
	273	else
	274	mvsdio_data->clock = 200000000;
e8b2b7ba	275	kirkwood_clk_ctrl \|= CGC_SDIO;
8235ee00 NP	276	kirkwood_sdio.dev.platform_data = mvsdio_data;
	277	platform_device_register(&kirkwood_sdio);
	278	}
	279
	280
18365d18 LB	281	/*****************************************************************************
	282	* SPI
	283	****************************************************************************/
18365d18 LB	284	void __init kirkwood_spi_init()
18365d18 LB	285	{
e8b2b7ba	286	kirkwood_clk_ctrl \|= CGC_RUNIT;
4574b886	287	orion_spi_init(SPI_PHYS_BASE);
18365d18 LB	288	}
	289
	290
6574e001 MM	291	/*****************************************************************************
	292	* I2C
	293	****************************************************************************/
6574e001 MM	294	void __init kirkwood_i2c_init(void)
6574e001 MM	295	{
aac7ffa3	296	orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
6574e001 MM	297	}
	298
	299
651c74c7 SB	300	/*****************************************************************************
	301	* UART0
	302	****************************************************************************/
651c74c7 SB	303
	304	void __init kirkwood_uart0_init(void)
	305	{
28a2b450	306	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
74c33576	307	IRQ_KIRKWOOD_UART_0, tclk);
651c74c7 SB	308	}
	309
	310
	311	/*****************************************************************************
	312	* UART1
	313	****************************************************************************/
651c74c7 SB	314	void __init kirkwood_uart1_init(void)
651c74c7 SB	315	{
28a2b450	316	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
74c33576	317	IRQ_KIRKWOOD_UART_1, tclk);
651c74c7 SB	318	}
651c74c7 SB	319
ae5c8c83 NP	320	/*****************************************************************************
	321	* Cryptographic Engines and Security Accelerator (CESA)
	322	****************************************************************************/
ae5c8c83 NP	323	void __init kirkwood_crypto_init(void)
	324	{
	325	kirkwood_clk_ctrl \|= CGC_CRYPTO;
44350061 AL	326	orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
44350061 AL	327	KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
ae5c8c83 NP	328	}
	329
	330
09c0ed2e SB	331	/*****************************************************************************
	332	* XOR0
	333	****************************************************************************/
2b45e05f	334	void __init kirkwood_xor0_init(void)
09c0ed2e	335	{
e8b2b7ba	336	kirkwood_clk_ctrl \|= CGC_XOR0;
ee962723	337
db33f4de	338	orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
ee962723	339	IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
09c0ed2e SB	340	}
	341
	342
	343	/*****************************************************************************
	344	* XOR1
	345	****************************************************************************/
2b45e05f	346	void __init kirkwood_xor1_init(void)
09c0ed2e	347	{
e8b2b7ba	348	kirkwood_clk_ctrl \|= CGC_XOR1;
ee962723 AL	349
	350	orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
	351	IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
09c0ed2e SB	352	}
	353
	354
054bd3f0 TR	355	/*****************************************************************************
	356	* Watchdog
	357	****************************************************************************/
2b45e05f	358	void __init kirkwood_wdt_init(void)
054bd3f0	359	{
4f04be62	360	orion_wdt_init();
054bd3f0 TR	361	}
	362
	363
651c74c7 SB	364	/*****************************************************************************
	365	* Time handling
	366	****************************************************************************/
4ee1f6b5 LB	367	void __init kirkwood_init_early(void)
	368	{
	369	orion_time_set_base(TIMER_VIRT_BASE);
	370	}
	371
79d4dd77 RS	372	int kirkwood_tclk;
79d4dd77 RS	373
9b8ebfec	374	static int __init kirkwood_find_tclk(void)
79d4dd77	375	{
b2b3dc2f RS	376	u32 dev, rev;
	377
	378	kirkwood_pcie_id(&dev, &rev);
1e4d2d3d	379
2fa0f939 SG	380	if (dev == MV88F6281_DEV_ID \|\| dev == MV88F6282_DEV_ID)
	381	if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
	382	return 200000000;
b2b3dc2f	383
79d4dd77 RS	384	return 166666667;
	385	}
	386
6de95c19	387	static void __init kirkwood_timer_init(void)
651c74c7	388	{
79d4dd77	389	kirkwood_tclk = kirkwood_find_tclk();
4ee1f6b5 LB	390
	391	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
	392	IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
651c74c7 SB	393	}
	394
	395	struct sys_timer kirkwood_timer = {
	396	.init = kirkwood_timer_init,
	397	};
	398
49106c72	399	/*****************************************************************************
	400	* Audio
	401	****************************************************************************/
	402	static struct resource kirkwood_i2s_resources[] = {
	403	[0] = {
	404	.start = AUDIO_PHYS_BASE,
	405	.end = AUDIO_PHYS_BASE + SZ_16K - 1,
	406	.flags = IORESOURCE_MEM,
	407	},
	408	[1] = {
	409	.start = IRQ_KIRKWOOD_I2S,
	410	.end = IRQ_KIRKWOOD_I2S,
	411	.flags = IORESOURCE_IRQ,
	412	},
	413	};
	414
	415	static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
49106c72	416	.burst = 128,
	417	};
	418
	419	static struct platform_device kirkwood_i2s_device = {
	420	.name = "kirkwood-i2s",
	421	.id = -1,
	422	.num_resources = ARRAY_SIZE(kirkwood_i2s_resources),
	423	.resource = kirkwood_i2s_resources,
	424	.dev = {
	425	.platform_data = &kirkwood_i2s_data,
	426	},
	427	};
	428
f0fba2ad	429	static struct platform_device kirkwood_pcm_device = {
c88e7b93	430	.name = "kirkwood-pcm-audio",
f0fba2ad LG	431	.id = -1,
	432	};
	433
49106c72	434	void __init kirkwood_audio_init(void)
	435	{
	436	kirkwood_clk_ctrl \|= CGC_AUDIO;
	437	platform_device_register(&kirkwood_i2s_device);
f0fba2ad	438	platform_device_register(&kirkwood_pcm_device);
49106c72	439	}
651c74c7 SB	440
	441	/*****************************************************************************
	442	* General
	443	****************************************************************************/
b2b3dc2f RS	444	/*
	445	* Identify device ID and revision.
	446	*/
2b45e05f	447	char * __init kirkwood_id(void)
651c74c7	448	{
b2b3dc2f RS	449	u32 dev, rev;
	450
	451	kirkwood_pcie_id(&dev, &rev);
	452
	453	if (dev == MV88F6281_DEV_ID) {
	454	if (rev == MV88F6281_REV_Z0)
	455	return "MV88F6281-Z0";
	456	else if (rev == MV88F6281_REV_A0)
	457	return "MV88F6281-A0";
aec1bad3 SG	458	else if (rev == MV88F6281_REV_A1)
aec1bad3 SG	459	return "MV88F6281-A1";
b2b3dc2f RS	460	else
	461	return "MV88F6281-Rev-Unsupported";
	462	} else if (dev == MV88F6192_DEV_ID) {
	463	if (rev == MV88F6192_REV_Z0)
	464	return "MV88F6192-Z0";
	465	else if (rev == MV88F6192_REV_A0)
	466	return "MV88F6192-A0";
1c2003a1 SB	467	else if (rev == MV88F6192_REV_A1)
1c2003a1 SB	468	return "MV88F6192-A1";
b2b3dc2f RS	469	else
	470	return "MV88F6192-Rev-Unsupported";
	471	} else if (dev == MV88F6180_DEV_ID) {
	472	if (rev == MV88F6180_REV_A0)
	473	return "MV88F6180-Rev-A0";
1c2003a1 SB	474	else if (rev == MV88F6180_REV_A1)
1c2003a1 SB	475	return "MV88F6180-Rev-A1";
b2b3dc2f RS	476	else
b2b3dc2f RS	477	return "MV88F6180-Rev-Unsupported";
1e4d2d3d SB	478	} else if (dev == MV88F6282_DEV_ID) {
	479	if (rev == MV88F6282_REV_A0)
	480	return "MV88F6282-Rev-A0";
a87d89e7 MM	481	else if (rev == MV88F6282_REV_A1)
a87d89e7 MM	482	return "MV88F6282-Rev-A1";
1e4d2d3d SB	483	else
1e4d2d3d SB	484	return "MV88F6282-Rev-Unsupported";
b2b3dc2f RS	485	} else {
b2b3dc2f RS	486	return "Device-Unknown";
651c74c7	487	}
651c74c7 SB	488	}
651c74c7 SB	489
2b45e05f	490	void __init kirkwood_l2_init(void)
13387603	491	{
4360bb41 RS	492	#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
	493	writel(readl(L2_CONFIG_REG) \| L2_WRITETHROUGH, L2_CONFIG_REG);
	494	feroceon_l2_init(1);
	495	#else
	496	writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
	497	feroceon_l2_init(0);
	498	#endif
13387603 SB	499	}
13387603 SB	500
651c74c7 SB	501	void __init kirkwood_init(void)
	502	{
	503	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
79d4dd77	504	kirkwood_id(), kirkwood_tclk);
651c74c7	505
2bf30108 LB	506	/*
	507	* Disable propagation of mbus errors to the CPU local bus,
	508	* as this causes mbus errors (which can occur for example
	509	* for PCI aborts) to throw CPU aborts, which we're not set
	510	* up to deal with.
	511	*/
	512	writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
	513
651c74c7 SB	514	kirkwood_setup_cpu_mbus();
	515
	516	#ifdef CONFIG_CACHE_FEROCEON_L2
4360bb41	517	kirkwood_l2_init();
651c74c7	518	#endif
5b99d534	519
2f129bf4 AL	520	/* Setup root of clk tree */
	521	kirkwood_clk_init();
	522
5b99d534 NP	523	/* internal devices that every board has */
5b99d534 NP	524	kirkwood_rtc_init();
054bd3f0	525	kirkwood_wdt_init();
5b99d534 NP	526	kirkwood_xor0_init();
5b99d534 NP	527	kirkwood_xor1_init();
ae5c8c83	528	kirkwood_crypto_init();
9c15364f EC	529
	530	#ifdef CONFIG_KEXEC
	531	kexec_reinit = kirkwood_enable_pcie;
	532	#endif
651c74c7	533	}
e8b2b7ba RK	534
	535	static int __init kirkwood_clock_gate(void)
	536	{
	537	unsigned int curr = readl(CLOCK_GATING_CTRL);
ffd58bd2	538	u32 dev, rev;
e8b2b7ba	539
ffd58bd2	540	kirkwood_pcie_id(&dev, &rev);
e8b2b7ba RK	541	printk(KERN_DEBUG "Gating clock of unused units\n");
	542	printk(KERN_DEBUG "before: 0x%08x\n", curr);
	543
	544	/* Make sure those units are accessible */
ffd58bd2	545	writel(curr \| CGC_SATA0 \| CGC_SATA1 \| CGC_PEX0 \| CGC_PEX1, CLOCK_GATING_CTRL);
e8b2b7ba RK	546
	547	/* For SATA: first shutdown the phy */
	548	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
	549	/* Disable PLL and IVREF */
	550	writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
	551	/* Disable PHY */
	552	writel(readl(SATA0_IF_CTRL) \| 0x200, SATA0_IF_CTRL);
	553	}
	554	if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
	555	/* Disable PLL and IVREF */
	556	writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
	557	/* Disable PHY */
	558	writel(readl(SATA1_IF_CTRL) \| 0x200, SATA1_IF_CTRL);
	559	}
	560
	561	/* For PCIe: first shutdown the phy */
	562	if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
	563	writel(readl(PCIE_LINK_CTRL) \| 0x10, PCIE_LINK_CTRL);
	564	while (1)
	565	if (readl(PCIE_STATUS) & 0x1)
	566	break;
	567	writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
	568	}
	569
ffd58bd2 SB	570	/* For PCIe 1: first shutdown the phy */
	571	if (dev == MV88F6282_DEV_ID) {
	572	if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
	573	writel(readl(PCIE1_LINK_CTRL) \| 0x10, PCIE1_LINK_CTRL);
	574	while (1)
	575	if (readl(PCIE1_STATUS) & 0x1)
	576	break;
	577	writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
	578	}
	579	} else /* keep this bit set for devices that don't have PCIe1 */
	580	kirkwood_clk_ctrl \|= CGC_PEX1;
	581
e8b2b7ba RK	582	/* Now gate clock the required units */
	583	writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
	584	printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
	585
	586	return 0;
	587	}
	588	late_initcall(kirkwood_clock_gate);
cb15dff4 RK	589
	590	void kirkwood_restart(char mode, const char *cmd)
	591	{
	592	/*
	593	* Enable soft reset to assert RSTOUTn.
	594	*/
	595	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
	596
	597	/*
	598	* Assert soft reset.
	599	*/
	600	writel(SOFT_RESET, SYSTEM_SOFT_RESET);
	601
	602	while (1)
	603	;
	604	}