Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/arm/mach-ixp4xx/common.c | |
3 | * | |
4 | * Generic code shared across all IXP4XX platforms | |
5 | * | |
6 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | |
7 | * | |
8 | * Copyright 2002 (c) Intel Corporation | |
9 | * Copyright 2003-2004 (c) MontaVista, Software, Inc. | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
1da177e4 LT |
16 | #include <linux/kernel.h> |
17 | #include <linux/mm.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/serial.h> | |
1da177e4 | 20 | #include <linux/tty.h> |
d052d1be | 21 | #include <linux/platform_device.h> |
1da177e4 | 22 | #include <linux/serial_core.h> |
1da177e4 LT |
23 | #include <linux/interrupt.h> |
24 | #include <linux/bitops.h> | |
25 | #include <linux/time.h> | |
26 | #include <linux/timex.h> | |
84904d0e | 27 | #include <linux/clocksource.h> |
e32f1502 | 28 | #include <linux/clockchips.h> |
fced80c7 | 29 | #include <linux/io.h> |
dc28094b | 30 | #include <linux/export.h> |
9dde0ae3 | 31 | #include <linux/gpio.h> |
f7b861b7 | 32 | #include <linux/cpu.h> |
38ff87f7 | 33 | #include <linux/sched_clock.h> |
1da177e4 | 34 | |
a09e64fb RK |
35 | #include <mach/udc.h> |
36 | #include <mach/hardware.h> | |
f449588c | 37 | #include <mach/io.h> |
1da177e4 | 38 | #include <asm/uaccess.h> |
1da177e4 LT |
39 | #include <asm/pgtable.h> |
40 | #include <asm/page.h> | |
41 | #include <asm/irq.h> | |
86dfe446 | 42 | #include <asm/system_misc.h> |
1da177e4 LT |
43 | |
44 | #include <asm/mach/map.h> | |
45 | #include <asm/mach/irq.h> | |
46 | #include <asm/mach/time.h> | |
47 | ||
ceb69a89 MP |
48 | static void __init ixp4xx_clocksource_init(void); |
49 | static void __init ixp4xx_clockevent_init(void); | |
e32f1502 | 50 | static struct clock_event_device clockevent_ixp4xx; |
f9a8ca1c | 51 | |
1da177e4 LT |
52 | /************************************************************************* |
53 | * IXP4xx chipset I/O mapping | |
54 | *************************************************************************/ | |
55 | static struct map_desc ixp4xx_io_desc[] __initdata = { | |
56 | { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ | |
13ec32f4 | 57 | .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT, |
87fe04bd | 58 | .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), |
1da177e4 LT |
59 | .length = IXP4XX_PERIPHERAL_REGION_SIZE, |
60 | .type = MT_DEVICE | |
61 | }, { /* Expansion Bus Config Registers */ | |
13ec32f4 | 62 | .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT, |
87fe04bd | 63 | .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), |
1da177e4 LT |
64 | .length = IXP4XX_EXP_CFG_REGION_SIZE, |
65 | .type = MT_DEVICE | |
66 | }, { /* PCI Registers */ | |
13ec32f4 | 67 | .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT, |
87fe04bd | 68 | .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), |
1da177e4 LT |
69 | .length = IXP4XX_PCI_CFG_REGION_SIZE, |
70 | .type = MT_DEVICE | |
f0cdb153 KH |
71 | }, { /* Queue Manager */ |
72 | .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT, | |
73 | .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS), | |
74 | .length = IXP4XX_QMGR_REGION_SIZE, | |
75 | .type = MT_DEVICE | |
5932ae3f | 76 | }, |
1da177e4 LT |
77 | }; |
78 | ||
79 | void __init ixp4xx_map_io(void) | |
80 | { | |
81 | iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc)); | |
82 | } | |
83 | ||
098e30f6 LW |
84 | /* |
85 | * GPIO-functions | |
86 | */ | |
87 | /* | |
88 | * The following converted to the real HW bits the gpio_line_config | |
89 | */ | |
90 | /* GPIO pin types */ | |
91 | #define IXP4XX_GPIO_OUT 0x1 | |
92 | #define IXP4XX_GPIO_IN 0x2 | |
93 | ||
94 | /* GPIO signal types */ | |
95 | #define IXP4XX_GPIO_LOW 0 | |
96 | #define IXP4XX_GPIO_HIGH 1 | |
97 | ||
98 | /* GPIO Clocks */ | |
99 | #define IXP4XX_GPIO_CLK_0 14 | |
100 | #define IXP4XX_GPIO_CLK_1 15 | |
101 | ||
102 | static void gpio_line_config(u8 line, u32 direction) | |
103 | { | |
104 | if (direction == IXP4XX_GPIO_IN) | |
105 | *IXP4XX_GPIO_GPOER |= (1 << line); | |
106 | else | |
107 | *IXP4XX_GPIO_GPOER &= ~(1 << line); | |
108 | } | |
109 | ||
110 | static void gpio_line_get(u8 line, int *value) | |
111 | { | |
112 | *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1; | |
113 | } | |
114 | ||
115 | static void gpio_line_set(u8 line, int value) | |
116 | { | |
117 | if (value == IXP4XX_GPIO_HIGH) | |
118 | *IXP4XX_GPIO_GPOUTR |= (1 << line); | |
119 | else if (value == IXP4XX_GPIO_LOW) | |
120 | *IXP4XX_GPIO_GPOUTR &= ~(1 << line); | |
121 | } | |
1da177e4 LT |
122 | |
123 | /************************************************************************* | |
124 | * IXP4xx chipset IRQ handling | |
125 | * | |
126 | * TODO: GPIO IRQs should be marked invalid until the user of the IRQ | |
127 | * (be it PCI or something else) configures that GPIO line | |
128 | * as an IRQ. | |
129 | **************************************************************************/ | |
bdf82b59 DS |
130 | enum ixp4xx_irq_type { |
131 | IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE | |
132 | }; | |
133 | ||
984d115b KH |
134 | /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */ |
135 | static unsigned long long ixp4xx_irq_edge = 0; | |
bdf82b59 DS |
136 | |
137 | /* | |
138 | * IRQ -> GPIO mapping table | |
139 | */ | |
6cc1b658 | 140 | static signed char irq2gpio[32] = { |
bdf82b59 DS |
141 | -1, -1, -1, -1, -1, -1, 0, 1, |
142 | -1, -1, -1, -1, -1, -1, -1, -1, | |
143 | -1, -1, -1, 2, 3, 4, 5, 6, | |
144 | 7, 8, 9, 10, 11, 12, -1, -1, | |
145 | }; | |
146 | ||
9dde0ae3 | 147 | static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) |
25735d10 MS |
148 | { |
149 | int irq; | |
150 | ||
151 | for (irq = 0; irq < 32; irq++) { | |
152 | if (irq2gpio[irq] == gpio) | |
153 | return irq; | |
154 | } | |
155 | return -EINVAL; | |
156 | } | |
25735d10 | 157 | |
ee04087a | 158 | static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type) |
bdf82b59 | 159 | { |
ee04087a | 160 | int line = irq2gpio[d->irq]; |
bdf82b59 DS |
161 | u32 int_style; |
162 | enum ixp4xx_irq_type irq_type; | |
163 | volatile u32 *int_reg; | |
164 | ||
165 | /* | |
166 | * Only for GPIO IRQs | |
167 | */ | |
168 | if (line < 0) | |
169 | return -EINVAL; | |
170 | ||