[linux-2.6-block.git] / arch / arm / mach-ixp2000 / ixdp2800.c

/*
 * arch/arm/mach-ixp2000/ixdp2800.c
 *
 * IXDP2800 platform support
 *
 * Original Author: Jeffrey Daly <jeffrey.daly@intel.com>
 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
 *
 * Copyright (C) 2002 Intel Corp.
 * Copyright (C) 2003-2004 MontaVista Software, Inc.
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/bitops.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/delay.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/system.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>

#include <asm/mach/pci.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/mach/flash.h>
#include <asm/mach/arch.h>

/*************************************************************************
 * IXDP2800 timer tick
 *************************************************************************/

static void __init ixdp2800_timer_init(void)
{
	ixp2000_init_time(50000000);
}

static struct sys_timer ixdp2800_timer = {
	.init		= ixdp2800_timer_init,
	.offset		= ixp2000_gettimeoffset,
};

/*************************************************************************
 * IXDP2800 PCI
 *************************************************************************/
static void __init ixdp2800_slave_disable_pci_master(void)
{
	*IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
}

static void __init ixdp2800_master_wait_for_slave(void)
{
	volatile u32 *addr;

	printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure "
			 "its BAR sizes\n");

	addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
					PCI_BASE_ADDRESS_1);
	do {
		*addr = 0xffffffff;
		cpu_relax();
	} while (*addr != 0xfe000008);

	addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
					PCI_BASE_ADDRESS_2);
	do {
		*addr = 0xffffffff;
		cpu_relax();
	} while (*addr != 0xc0000008);

	/*
	 * Configure the slave's SDRAM BAR by hand.
	 */
	*addr = 0x40000008;
}

static void __init ixdp2800_slave_wait_for_master_enable(void)
{
	printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n");

	while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0)
		cpu_relax();
}

void __init ixdp2800_pci_preinit(void)
{
	printk("ixdp2x00_pci_preinit called\n");

	*IXP2000_PCI_ADDR_EXT = 0x0001e000;

	if (!ixdp2x00_master_npu())
		ixdp2800_slave_disable_pci_master();

	*IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff;
	*IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff;

	ixp2000_pci_preinit();

	if (ixdp2x00_master_npu()) {
		/*
		 * Wait until the slave set its SRAM/SDRAM BAR sizes
		 * correctly before we proceed to scan and enumerate
		 * the bus.
		 */
		ixdp2800_master_wait_for_slave();

		/*
		 * We configure the SDRAM BARs by hand because they
		 * are 1G and fall outside of the regular allocated
		 * PCI address space.
		 */
		*IXP2000_PCI_SDRAM_BAR = 0x00000008;
	} else {
		/*
		 * Wait for the master to complete scanning the bus
		 * and assigning resources before we proceed to scan
		 * the bus ourselves.  Set pci=firmware to honor the
		 * master's resource assignment.
		 */
		ixdp2800_slave_wait_for_master_enable();
		pcibios_setup("firmware");
	}
}

/*
 * We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside
 * of the regular PCI window, because there's only 512M of outbound PCI
 * memory window on each IXP, while we need 1G for each of the BARs.
 */
static void __devinit ixp2800_pci_fixup(struct pci_dev *dev)
{
	if (machine_is_ixdp2800()) {
		dev->resource[2].start = 0;
		dev->resource[2].end   = 0;
		dev->resource[2].flags = 0;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup);

static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys)
{
	sys->mem_offset = 0x00000000;

	ixp2000_pci_setup(nr, sys);

	return 1;
}

static int __init ixdp2800_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	if (ixdp2x00_master_npu()) {

		/*
		 * Root bus devices.  Slave NPU is only one with interrupt.
		 * Everything else, we just return -1 which is invalid.
		 */
		if(!dev->bus->self) {
			if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
				return IRQ_IXDP2800_INGRESS_NPU;

			return -1;
		}

		/*
		 * Bridge behind the PMC slot.
		 */
		if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
			dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
			!dev->bus->parent->self->bus->parent)
				  return IRQ_IXDP2800_PMC;

		/*
		 * Device behind the first bridge
		 */
		if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
			switch(dev->devfn) {
				case IXDP2X00_PMC_DEVFN:
					return IRQ_IXDP2800_PMC;	
			
				case IXDP2800_MASTER_ENET_DEVFN:
					return IRQ_IXDP2800_EGRESS_ENET;

				case IXDP2800_SWITCH_FABRIC_DEVFN:
					return IRQ_IXDP2800_FABRIC;
			}
		}

		return -1;
	} else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
}

static void __init ixdp2800_master_enable_slave(void)
{
	volatile u32 *addr;

	printk(KERN_INFO "IXDP2800: enabling slave NPU\n");

	addr = (volatile u32 *)ixp2000_pci_config_addr(0,
					IXDP2X00_SLAVE_NPU_DEVFN,
					PCI_COMMAND);

	*addr |= PCI_COMMAND_MASTER;
}

static void __init ixdp2800_master_wait_for_slave_bus_scan(void)
{
	volatile u32 *addr;

	printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n");

	addr = (volatile u32 *)ixp2000_pci_config_addr(0,
					IXDP2X00_SLAVE_NPU_DEVFN,
					PCI_COMMAND);
	while ((*addr & PCI_COMMAND_MEMORY) == 0)
		cpu_relax();
}

static void __init ixdp2800_slave_signal_bus_scan_completion(void)
{
	printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n");
	*IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY;
}

static void __init ixdp2800_pci_postinit(void)
{
	if (!ixdp2x00_master_npu()) {
		ixdp2x00_slave_pci_postinit();
		ixdp2800_slave_signal_bus_scan_completion();
	}
}

struct __initdata hw_pci ixdp2800_pci __initdata = {
	.nr_controllers	= 1,
	.setup		= ixdp2800_pci_setup,
	.preinit	= ixdp2800_pci_preinit,
	.postinit	= ixdp2800_pci_postinit,
	.scan		= ixp2000_pci_scan_bus,
	.map_irq	= ixdp2800_pci_map_irq,
};

int __init ixdp2800_pci_init(void)
{
	if (machine_is_ixdp2800()) {
		struct pci_dev *dev;

		pci_common_init(&ixdp2800_pci);
		if (ixdp2x00_master_npu()) {
			dev = pci_find_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
			pci_remove_bus_device(dev);

			ixdp2800_master_enable_slave();
			ixdp2800_master_wait_for_slave_bus_scan();
		} else {
			dev = pci_find_slot(1, IXDP2800_MASTER_ENET_DEVFN);
			pci_remove_bus_device(dev);
		}
	}

	return 0;
}

subsys_initcall(ixdp2800_pci_init);

void ixdp2800_init_irq(void)
{
	ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS);
}

MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.phys_ram	= 0x00000000,
	.phys_io	= IXP2000_UART_PHYS_BASE,
	.io_pg_offst	= ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
	.boot_params	= 0x00000100,
	.map_io		= ixdp2x00_map_io,
	.init_irq	= ixdp2800_init_irq,
	.timer		= &ixdp2800_timer,
	.init_machine	= ixdp2x00_init_machine,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/arm/mach-ixp2000/ixdp2800.c
	3	*
	4	* IXDP2800 platform support
	5	*
	6	* Original Author: Jeffrey Daly <jeffrey.daly@intel.com>
	7	* Maintainer: Deepak Saxena <dsaxena@plexity.net>
	8	*
	9	* Copyright (C) 2002 Intel Corp.
	10	* Copyright (C) 2003-2004 MontaVista Software, Inc.
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License as published by the
	14	* Free Software Foundation; either version 2 of the License, or (at your
	15	* option) any later version.
	16	*/
	17	#include <linux/config.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/mm.h>
	21	#include <linux/sched.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/device.h>
	24	#include <linux/bitops.h>
	25	#include <linux/pci.h>
	26	#include <linux/ioport.h>
	27	#include <linux/slab.h>
	28	#include <linux/delay.h>
	29
	30	#include <asm/io.h>
	31	#include <asm/irq.h>
	32	#include <asm/pgtable.h>
	33	#include <asm/page.h>
	34	#include <asm/system.h>
	35	#include <asm/hardware.h>
	36	#include <asm/mach-types.h>
	37
	38	#include <asm/mach/pci.h>
	39	#include <asm/mach/map.h>
	40	#include <asm/mach/irq.h>
	41	#include <asm/mach/time.h>
	42	#include <asm/mach/flash.h>
	43	#include <asm/mach/arch.h>
	44
1da177e4 LT	45	/*************************************************************************
	46	* IXDP2800 timer tick
	47	*************************************************************************/
	48
	49	static void __init ixdp2800_timer_init(void)
	50	{
	51	ixp2000_init_time(50000000);
	52	}
	53
	54	static struct sys_timer ixdp2800_timer = {
	55	.init = ixdp2800_timer_init,
	56	.offset = ixp2000_gettimeoffset,
	57	};
	58
	59	/*************************************************************************
	60	* IXDP2800 PCI
	61	*************************************************************************/
53e173f6 LB	62	static void __init ixdp2800_slave_disable_pci_master(void)
	63	{
	64	*IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY);
	65	}
	66
	67	static void __init ixdp2800_master_wait_for_slave(void)
	68	{
	69	volatile u32 *addr;
	70
	71	printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure "
	72	"its BAR sizes\n");
	73
	74	addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
	75	PCI_BASE_ADDRESS_1);
	76	do {
	77	*addr = 0xffffffff;
	78	cpu_relax();
	79	} while (*addr != 0xfe000008);
	80
	81	addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
	82	PCI_BASE_ADDRESS_2);
	83	do {
	84	*addr = 0xffffffff;
	85	cpu_relax();
	86	} while (*addr != 0xc0000008);
	87
	88	/*
	89	* Configure the slave's SDRAM BAR by hand.
	90	*/
	91	*addr = 0x40000008;
	92	}
	93
	94	static void __init ixdp2800_slave_wait_for_master_enable(void)
	95	{
	96	printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n");
	97
	98	while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0)
	99	cpu_relax();
	100	}
	101
1da177e4 LT	102	void __init ixdp2800_pci_preinit(void)
	103	{
	104	printk("ixdp2x00_pci_preinit called\n");
	105
53e173f6 LB	106	*IXP2000_PCI_ADDR_EXT = 0x0001e000;
	107
	108	if (!ixdp2x00_master_npu())
	109	ixdp2800_slave_disable_pci_master();
1da177e4	110
1da177e4	111	*IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff;
53e173f6	112	*IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff;
1da177e4 LT	113
1da177e4 LT	114	ixp2000_pci_preinit();
53e173f6 LB	115
	116	if (ixdp2x00_master_npu()) {
	117	/*
	118	* Wait until the slave set its SRAM/SDRAM BAR sizes
	119	* correctly before we proceed to scan and enumerate
	120	* the bus.
	121	*/
	122	ixdp2800_master_wait_for_slave();
	123
	124	/*
	125	* We configure the SDRAM BARs by hand because they
	126	* are 1G and fall outside of the regular allocated
	127	* PCI address space.
	128	*/
	129	*IXP2000_PCI_SDRAM_BAR = 0x00000008;
	130	} else {
	131	/*
	132	* Wait for the master to complete scanning the bus
	133	* and assigning resources before we proceed to scan
	134	* the bus ourselves. Set pci=firmware to honor the
	135	* master's resource assignment.
	136	*/
	137	ixdp2800_slave_wait_for_master_enable();
	138	pcibios_setup("firmware");
	139	}
1da177e4 LT	140	}
1da177e4 LT	141
53e173f6 LB	142	/*
	143	* We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside
	144	* of the regular PCI window, because there's only 512M of outbound PCI
	145	* memory window on each IXP, while we need 1G for each of the BARs.
	146	*/
	147	static void __devinit ixp2800_pci_fixup(struct pci_dev *dev)
	148	{
	149	if (machine_is_ixdp2800()) {
	150	dev->resource[2].start = 0;
	151	dev->resource[2].end = 0;
	152	dev->resource[2].flags = 0;
	153	}
	154	}
	155	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup);
	156
	157	static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys)
1da177e4 LT	158	{
	159	sys->mem_offset = 0x00000000;
	160
	161	ixp2000_pci_setup(nr, sys);
	162
	163	return 1;
	164	}
	165
	166	static int __init ixdp2800_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	167	{
	168	if (ixdp2x00_master_npu()) {
	169
	170	/*
	171	* Root bus devices. Slave NPU is only one with interrupt.
	172	* Everything else, we just return -1 which is invalid.
	173	*/
	174	if(!dev->bus->self) {
	175	if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
	176	return IRQ_IXDP2800_INGRESS_NPU;
	177
	178	return -1;
	179	}
	180
	181	/*
	182	* Bridge behind the PMC slot.
	183	*/
	184	if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
	185	dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
	186	!dev->bus->parent->self->bus->parent)
	187	return IRQ_IXDP2800_PMC;
	188
	189	/*
	190	* Device behind the first bridge
	191	*/
	192	if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
	193	switch(dev->devfn) {
	194	case IXDP2X00_PMC_DEVFN:
	195	return IRQ_IXDP2800_PMC;
	196
	197	case IXDP2800_MASTER_ENET_DEVFN:
	198	return IRQ_IXDP2800_EGRESS_ENET;
	199
	200	case IXDP2800_SWITCH_FABRIC_DEVFN:
	201	return IRQ_IXDP2800_FABRIC;
	202	}
	203	}
	204
	205	return -1;
	206	} else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
	207	}
	208
53e173f6	209	static void __init ixdp2800_master_enable_slave(void)
1da177e4	210	{
53e173f6	211	volatile u32 *addr;
1da177e4	212
53e173f6 LB	213	printk(KERN_INFO "IXDP2800: enabling slave NPU\n");
	214
	215	addr = (volatile u32 *)ixp2000_pci_config_addr(0,
	216	IXDP2X00_SLAVE_NPU_DEVFN,
	217	PCI_COMMAND);
	218
	219	*addr \|= PCI_COMMAND_MASTER;
	220	}
1da177e4	221
53e173f6 LB	222	static void __init ixdp2800_master_wait_for_slave_bus_scan(void)
	223	{
	224	volatile u32 *addr;
	225
	226	printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n");
	227
	228	addr = (volatile u32 *)ixp2000_pci_config_addr(0,
	229	IXDP2X00_SLAVE_NPU_DEVFN,
	230	PCI_COMMAND);
	231	while ((*addr & PCI_COMMAND_MEMORY) == 0)
	232	cpu_relax();
	233	}
	234
	235	static void __init ixdp2800_slave_signal_bus_scan_completion(void)
	236	{
	237	printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n");
	238	*IXP2000_PCI_CMDSTAT \|= PCI_COMMAND_MEMORY;
	239	}
	240
	241	static void __init ixdp2800_pci_postinit(void)
	242	{
	243	if (!ixdp2x00_master_npu()) {
1da177e4	244	ixdp2x00_slave_pci_postinit();
53e173f6	245	ixdp2800_slave_signal_bus_scan_completion();
1da177e4 LT	246	}
	247	}
	248
53e173f6	249	struct __initdata hw_pci ixdp2800_pci __initdata = {
1da177e4 LT	250	.nr_controllers = 1,
	251	.setup = ixdp2800_pci_setup,
	252	.preinit = ixdp2800_pci_preinit,
	253	.postinit = ixdp2800_pci_postinit,
	254	.scan = ixp2000_pci_scan_bus,
	255	.map_irq = ixdp2800_pci_map_irq,
	256	};
	257
	258	int __init ixdp2800_pci_init(void)
	259	{
53e173f6 LB	260	if (machine_is_ixdp2800()) {
	261	struct pci_dev *dev;
	262
1da177e4	263	pci_common_init(&ixdp2800_pci);
53e173f6 LB	264	if (ixdp2x00_master_npu()) {
	265	dev = pci_find_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
	266	pci_remove_bus_device(dev);
	267
	268	ixdp2800_master_enable_slave();
	269	ixdp2800_master_wait_for_slave_bus_scan();
	270	} else {
	271	dev = pci_find_slot(1, IXDP2800_MASTER_ENET_DEVFN);
	272	pci_remove_bus_device(dev);
	273	}
	274	}
1da177e4 LT	275
	276	return 0;
	277	}
	278
	279	subsys_initcall(ixdp2800_pci_init);
	280
	281	void ixdp2800_init_irq(void)
	282	{
	283	ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS);
	284	}
	285
	286	MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
e9dea0c6 RK	287	/* Maintainer: MontaVista Software, Inc. */
	288	.phys_ram = 0x00000000,
	289	.phys_io = IXP2000_UART_PHYS_BASE,
	290	.io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
	291	.boot_params = 0x00000100,
	292	.map_io = ixdp2x00_map_io,
	293	.init_irq = ixdp2800_init_irq,
1da177e4	294	.timer = &ixdp2800_timer,
e9dea0c6	295	.init_machine = ixdp2x00_init_machine,
1da177e4 LT	296	MACHINE_END
1da177e4 LT	297