[linux-2.6-block.git] / arch / arm / mach-iop32x / irq.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * arch/arm/mach-iop32x/irq.c
 *
 * Generic IOP32X IRQ handling functionality
 *
 * Author: Rory Bolt <rorybolt@pacbell.net>
 * Copyright (C) 2002 Rory Bolt
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include "hardware.h"

static u32 iop32x_mask;

static void intctl_write(u32 val)
{
	asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
}

static void intstr_write(u32 val)
{
	asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
}

static void
iop32x_irq_mask(struct irq_data *d)
{
	iop32x_mask &= ~(1 << d->irq);
	intctl_write(iop32x_mask);
}

static void
iop32x_irq_unmask(struct irq_data *d)
{
	iop32x_mask |= 1 << d->irq;
	intctl_write(iop32x_mask);
}

struct irq_chip ext_chip = {
	.name		= "IOP32x",
	.irq_ack	= iop32x_irq_mask,
	.irq_mask	= iop32x_irq_mask,
	.irq_unmask	= iop32x_irq_unmask,
};

void __init iop32x_init_irq(void)
{
	int i;

	iop_init_cp6_handler();

	intctl_write(0);
	intstr_write(0);
	if (machine_is_glantank() ||
	    machine_is_iq80321() ||
	    machine_is_iq31244() ||
	    machine_is_n2100() ||
	    machine_is_em7210())
		*IOP3XX_PCIIRSR = 0x0f;

	for (i = 0; i < NR_IRQS; i++) {
		irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
		irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
	}
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4	2	/*
c852ac80	3	* arch/arm/mach-iop32x/irq.c
1da177e4	4	*
3f7e5815	5	* Generic IOP32X IRQ handling functionality
1da177e4 LT	6	*
	7	* Author: Rory Bolt <rorybolt@pacbell.net>
	8	* Copyright (C) 2002 Rory Bolt
1da177e4	9	*/
c852ac80	10
1da177e4 LT	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/list.h>
1da177e4 LT	14	#include <asm/mach/irq.h>
1da177e4 LT	15	#include <asm/irq.h>
1da177e4 LT	16	#include <asm/mach-types.h>
1da177e4 LT	17
a1f487d7 AB	18	#include "hardware.h"
a1f487d7 AB	19
c852ac80	20	static u32 iop32x_mask;
1da177e4	21
d73d8011	22	static void intctl_write(u32 val)
1da177e4	23	{
c852ac80	24	asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
1da177e4 LT	25	}
1da177e4 LT	26
d73d8011	27	static void intstr_write(u32 val)
1da177e4	28	{
c852ac80	29	asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
1da177e4 LT	30	}
	31
	32	static void
465b4079	33	iop32x_irq_mask(struct irq_data *d)
1da177e4	34	{
465b4079	35	iop32x_mask &= ~(1 << d->irq);
c852ac80	36	intctl_write(iop32x_mask);
1da177e4 LT	37	}
	38
	39	static void
465b4079	40	iop32x_irq_unmask(struct irq_data *d)
1da177e4	41	{
465b4079	42	iop32x_mask \|= 1 << d->irq;
c852ac80	43	intctl_write(iop32x_mask);
1da177e4 LT	44	}
1da177e4 LT	45
38c677cb	46	struct irq_chip ext_chip = {
465b4079 LB	47	.name = "IOP32x",
	48	.irq_ack = iop32x_irq_mask,
	49	.irq_mask = iop32x_irq_mask,
	50	.irq_unmask = iop32x_irq_unmask,
1da177e4 LT	51	};
1da177e4 LT	52
c852ac80	53	void __init iop32x_init_irq(void)
1da177e4	54	{
c852ac80	55	int i;
1da177e4	56
588ef769 DW	57	iop_init_cp6_handler();
588ef769 DW	58
c852ac80 LB	59	intctl_write(0);
c852ac80 LB	60	intstr_write(0);
0c92e830 LB	61	if (machine_is_glantank() \|\|
0c92e830 LB	62	machine_is_iq80321() \|\|
e60d07b6	63	machine_is_iq31244() \|\|
a8135fcf AP	64	machine_is_n2100() \|\|
a8135fcf AP	65	machine_is_em7210())
7e9740b1	66	*IOP3XX_PCIIRSR = 0x0f;
1da177e4	67
c852ac80	68	for (i = 0; i < NR_IRQS; i++) {
f38c02f3	69	irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
e8d36d5d	70	irq_clear_status_flags(i, IRQ_NOREQUEST \| IRQ_NOPROBE);
1da177e4 LT	71	}
1da177e4 LT	72	}