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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
c852ac80 | 2 | /* |
a09e64fb | 3 | * arch/arm/mach-iop32x/include/mach/iop32x.h |
c852ac80 LB |
4 | * |
5 | * Intel IOP32X Chip definitions | |
6 | * | |
7 | * Author: Rory Bolt <rorybolt@pacbell.net> | |
8 | * Copyright (C) 2002 Rory Bolt | |
9 | * Copyright (C) 2004 Intel Corp. | |
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10 | */ |
11 | ||
12 | #ifndef __IOP32X_H | |
13 | #define __IOP32X_H | |
14 | ||
15 | /* | |
16 | * Peripherals that are shared between the iop32x and iop33x but | |
17 | * located at different addresses. | |
18 | */ | |
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19 | #define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) |
20 | ||
21 | #include <asm/hardware/iop3xx.h> | |
22 | ||
e90ddd81 DW |
23 | /* ATU Parameters |
24 | * set up a 1:1 bus to physical ram relationship | |
25 | * w/ physical ram on top of pci in the memory map | |
26 | */ | |
27 | #define IOP32X_MAX_RAM_SIZE 0x40000000UL | |
28 | #define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE | |
29 | #define IOP3XX_PCI_LOWER_MEM_BA 0x80000000 | |
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30 | |
31 | #endif |