[linux-2.6-block.git] / arch / arm / mach-imx / time.c

/*
 *  linux/arch/arm/plat-mxc/time.c
 *
 *  Copyright (C) 2000-2001 Deep Blue Solutions
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
 *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <soc/imx/timer.h>

#include <asm/mach/time.h>

#include "common.h"
#include "hardware.h"

/*
 * There are 4 versions of the timer hardware on Freescale MXC hardware.
 *  - MX1/MXL
 *  - MX21, MX27.
 *  - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
 *  - MX6DL, MX6SX, MX6Q(rev1.1+)
 */

/* defines common for all i.MX */
#define MXC_TCTL		0x00
#define MXC_TCTL_TEN		(1 << 0) /* Enable module */
#define MXC_TPRER		0x04

/* MX1, MX21, MX27 */
#define MX1_2_TCTL_CLK_PCLK1	(1 << 1)
#define MX1_2_TCTL_IRQEN	(1 << 4)
#define MX1_2_TCTL_FRR		(1 << 8)
#define MX1_2_TCMP		0x08
#define MX1_2_TCN		0x10
#define MX1_2_TSTAT		0x14

/* MX21, MX27 */
#define MX2_TSTAT_CAPT		(1 << 1)
#define MX2_TSTAT_COMP		(1 << 0)

/* MX31, MX35, MX25, MX5, MX6 */
#define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG		(1 << 6)
#define V2_TCTL_CLK_PER		(2 << 6)
#define V2_TCTL_CLK_OSC_DIV8	(5 << 6)
#define V2_TCTL_FRR		(1 << 9)
#define V2_TCTL_24MEN		(1 << 10)
#define V2_TPRER_PRE24M		12
#define V2_IR			0x0c
#define V2_TSTAT		0x08
#define V2_TSTAT_OF1		(1 << 0)
#define V2_TCN			0x24
#define V2_TCMP			0x10

#define V2_TIMER_RATE_OSC_DIV8	3000000

#define timer_is_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
#define timer_is_v2()	(!timer_is_v1())

static struct clock_event_device clockevent_mxc;
static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;

struct imx_timer {
	enum imx_gpt_type type;
	void __iomem *base;
	int irq;
	struct clk *clk_per;
	struct clk *clk_ipg;
	const struct imx_gpt_data *gpt;
};

struct imx_gpt_data {
	void (*gpt_setup_tctl)(struct imx_timer *imxtm);
};

static void __iomem *timer_base;

static inline void gpt_irq_disable(void)
{
	unsigned int tmp;

	if (timer_is_v2())
		writel_relaxed(0, timer_base + V2_IR);
	else {
		tmp = readl_relaxed(timer_base + MXC_TCTL);
		writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
	}
}

static inline void gpt_irq_enable(void)
{
	if (timer_is_v2())
		writel_relaxed(1<<0, timer_base + V2_IR);
	else {
		writel_relaxed(readl_relaxed(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
			timer_base + MXC_TCTL);
	}
}

static void gpt_irq_acknowledge(void)
{
	if (timer_is_v1()) {
		if (cpu_is_mx1())
			writel_relaxed(0, timer_base + MX1_2_TSTAT);
		else
			writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
				timer_base + MX1_2_TSTAT);
	} else if (timer_is_v2())
		writel_relaxed(V2_TSTAT_OF1, timer_base + V2_TSTAT);
}

static void __iomem *sched_clock_reg;

static u64 notrace mxc_read_sched_clock(void)
{
	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
}

static struct delay_timer imx_delay_timer;

static unsigned long imx_read_current_timer(void)
{
	return readl_relaxed(sched_clock_reg);
}

static int __init mxc_clocksource_init(struct imx_timer *imxtm)
{
	unsigned int c = clk_get_rate(imxtm->clk_per);
	void __iomem *reg = imxtm->base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);

	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	imx_delay_timer.freq = c;
	register_current_timer_delay(&imx_delay_timer);

	sched_clock_reg = reg;

	sched_clock_register(mxc_read_sched_clock, 32, c);
	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
			clocksource_mmio_readl_up);
}

/* clock event */

static int mx1_2_set_next_event(unsigned long evt,
			      struct clock_event_device *unused)
{
	unsigned long tcmp;

	tcmp = readl_relaxed(timer_base + MX1_2_TCN) + evt;

	writel_relaxed(tcmp, timer_base + MX1_2_TCMP);

	return (int)(tcmp - readl_relaxed(timer_base + MX1_2_TCN)) < 0 ?
				-ETIME : 0;
}

static int v2_set_next_event(unsigned long evt,
			      struct clock_event_device *unused)
{
	unsigned long tcmp;

	tcmp = readl_relaxed(timer_base + V2_TCN) + evt;

	writel_relaxed(tcmp, timer_base + V2_TCMP);

	return evt < 0x7fffffff &&
		(int)(tcmp - readl_relaxed(timer_base + V2_TCN)) < 0 ?
				-ETIME : 0;
}

#ifdef DEBUG
static const char *clock_event_mode_label[] = {
	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	[CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
	[CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED",
	[CLOCK_EVT_MODE_RESUME]   = "CLOCK_EVT_MODE_RESUME",
};
#endif /* DEBUG */

static void mxc_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	unsigned long flags;

	/*
	 * The timer interrupt generation is disabled at least
	 * for enough time to call mxc_set_next_event()
	 */
	local_irq_save(flags);

	/* Disable interrupt in GPT module */
	gpt_irq_disable();

	if (mode != clockevent_mode) {
		/* Set event time into far-far future */
		if (timer_is_v2())
			writel_relaxed(readl_relaxed(timer_base + V2_TCN) - 3,
					timer_base + V2_TCMP);
		else
			writel_relaxed(readl_relaxed(timer_base + MX1_2_TCN) - 3,
					timer_base + MX1_2_TCMP);

		/* Clear pending interrupt */
		gpt_irq_acknowledge();
	}

#ifdef DEBUG
	printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
		clock_event_mode_label[clockevent_mode],
		clock_event_mode_label[mode]);
#endif /* DEBUG */

	/* Remember timer mode */
	clockevent_mode = mode;
	local_irq_restore(flags);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
				"supported for i.MX\n");
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	/*
	 * Do not put overhead of interrupt enable/disable into
	 * mxc_set_next_event(), the core has about 4 minutes
	 * to call mxc_set_next_event() or shutdown clock after
	 * mode switching
	 */
		local_irq_save(flags);
		gpt_irq_enable();
		local_irq_restore(flags);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_RESUME:
		/* Left event sources disabled, no more interrupts appear */
		break;
	}
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_mxc;
	uint32_t tstat;

	if (timer_is_v2())
		tstat = readl_relaxed(timer_base + V2_TSTAT);
	else
		tstat = readl_relaxed(timer_base + MX1_2_TSTAT);

	gpt_irq_acknowledge();

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mxc_timer_irq = {
	.name		= "i.MX Timer Tick",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= mxc_timer_interrupt,
};

static struct clock_event_device clockevent_mxc = {
	.name		= "mxc_timer1",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= mxc_set_mode,
	.set_next_event	= mx1_2_set_next_event,
	.rating		= 200,
};

static int __init mxc_clockevent_init(struct imx_timer *imxtm)
{
	if (timer_is_v2())
		clockevent_mxc.set_next_event = v2_set_next_event;

	clockevent_mxc.cpumask = cpumask_of(0);
	clockevents_config_and_register(&clockevent_mxc,
					clk_get_rate(imxtm->clk_per),
					0xff, 0xfffffffe);

	return 0;
}

static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl

static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
	else
		tctl_val |= V2_TCTL_CLK_PER;

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
		/* 24 / 8 = 3 MHz */
		writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
		tctl_val |= V2_TCTL_24MEN;
	} else {
		tctl_val |= V2_TCTL_CLK_PER;
	}

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static const struct imx_gpt_data imx1_gpt_data = {
	.gpt_setup_tctl = imx1_gpt_setup_tctl,
};

static const struct imx_gpt_data imx21_gpt_data = {
	.gpt_setup_tctl = imx21_gpt_setup_tctl,
};

static const struct imx_gpt_data imx31_gpt_data = {
	.gpt_setup_tctl = imx31_gpt_setup_tctl,
};

static const struct imx_gpt_data imx6dl_gpt_data = {
	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
};

static void __init _mxc_timer_init(struct imx_timer *imxtm)
{
	/* Temporary */
	timer_base = imxtm->base;

	switch (imxtm->type) {
	case GPT_TYPE_IMX1:
		imxtm->gpt = &imx1_gpt_data;
		break;
	case GPT_TYPE_IMX21:
		imxtm->gpt = &imx21_gpt_data;
		break;
	case GPT_TYPE_IMX31:
		imxtm->gpt = &imx31_gpt_data;
		break;
	case GPT_TYPE_IMX6DL:
		imxtm->gpt = &imx6dl_gpt_data;
		break;
	default:
		BUG();
	}

	if (IS_ERR(imxtm->clk_per)) {
		pr_err("i.MX timer: unable to get clk\n");
		return;
	}

	if (!IS_ERR(imxtm->clk_ipg))
		clk_prepare_enable(imxtm->clk_ipg);

	clk_prepare_enable(imxtm->clk_per);

	/*
	 * Initialise to a known state (all timers off, and timing reset)
	 */

	writel_relaxed(0, imxtm->base + MXC_TCTL);
	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */

	imxtm->gpt->gpt_setup_tctl(imxtm);

	/* init and register the timer to the framework */
	mxc_clocksource_init(imxtm);
	mxc_clockevent_init(imxtm);

	/* Make irqs happen */
	setup_irq(imxtm->irq, &mxc_timer_irq);
}

void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
{
	struct imx_timer *imxtm;

	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	BUG_ON(!imxtm);

	imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
	imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");

	imxtm->base = ioremap(pbase, SZ_4K);
	BUG_ON(!imxtm->base);

	imxtm->type = type;

	_mxc_timer_init(imxtm);
}

static void __init mxc_timer_init_dt(struct device_node *np,  enum imx_gpt_type type)
{
	struct imx_timer *imxtm;
	static int initialized;

	/* Support one instance only */
	if (initialized)
		return;

	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	BUG_ON(!imxtm);

	imxtm->base = of_iomap(np, 0);
	WARN_ON(!imxtm->base);
	imxtm->irq = irq_of_parse_and_map(np, 0);

	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");

	/* Try osc_per first, and fall back to per otherwise */
	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	if (IS_ERR(imxtm->clk_per))
		imxtm->clk_per = of_clk_get_by_name(np, "per");

	imxtm->type = type;

	_mxc_timer_init(imxtm);

	initialized = 1;
}

static void __init imx1_timer_init_dt(struct device_node *np)
{
	mxc_timer_init_dt(np, GPT_TYPE_IMX1);
}

static void __init imx21_timer_init_dt(struct device_node *np)
{
	mxc_timer_init_dt(np, GPT_TYPE_IMX21);
}

static void __init imx31_timer_init_dt(struct device_node *np)
{
	enum imx_gpt_type type = GPT_TYPE_IMX31;

	/*
	 * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	 * GPT device, while they actually have different programming model.
	 * This is a workaround to keep the existing i.MX6DL/S DTBs continue
	 * working with the new kernel.
	 */
	if (of_machine_is_compatible("fsl,imx6dl"))
		type = GPT_TYPE_IMX6DL;

	mxc_timer_init_dt(np, type);
}

static void __init imx6dl_timer_init_dt(struct device_node *np)
{
	mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
}

CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
Commit	Line	Data
d0f349fb JB	1	/*
	2	* linux/arch/arm/plat-mxc/time.c
	3	*
	4	* Copyright (C) 2000-2001 Deep Blue Solutions
	5	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	6	* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	7	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version 2
	12	* of the License, or (at your option) any later version.
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	21	* MA 02110-1301, USA.
	22	*/
	23
	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
	26	#include <linux/clockchips.h>
	27	#include <linux/clk.h>
1119c84a	28	#include <linux/delay.h>
821dc4df	29	#include <linux/err.h>
38ff87f7	30	#include <linux/sched_clock.h>
6dd74782	31	#include <linux/slab.h>
876292d6 GC	32	#include <linux/of.h>
	33	#include <linux/of_address.h>
	34	#include <linux/of_irq.h>
0931aff7	35	#include <soc/imx/timer.h>
d0f349fb	36
d0f349fb	37	#include <asm/mach/time.h>
e3372474 SG	38
e3372474 SG	39	#include "common.h"
50f2de61	40	#include "hardware.h"
ec996ba9	41
0f3332c4	42	/*
65d0a16d SW	43	* There are 4 versions of the timer hardware on Freescale MXC hardware.
	44	* - MX1/MXL
	45	* - MX21, MX27.
	46	* - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
	47	* - MX6DL, MX6SX, MX6Q(rev1.1+)
0f3332c4 SH	48	*/
0f3332c4 SH	49
ec996ba9 SH	50	/* defines common for all i.MX */
ec996ba9 SH	51	#define MXC_TCTL 0x00
0f3332c4	52	#define MXC_TCTL_TEN (1 << 0) /* Enable module */
ec996ba9 SH	53	#define MXC_TPRER 0x04
	54
	55	/* MX1, MX21, MX27 */
	56	#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
	57	#define MX1_2_TCTL_IRQEN (1 << 4)
	58	#define MX1_2_TCTL_FRR (1 << 8)
	59	#define MX1_2_TCMP 0x08
	60	#define MX1_2_TCN 0x10
	61	#define MX1_2_TSTAT 0x14
	62
	63	/* MX21, MX27 */
	64	#define MX2_TSTAT_CAPT (1 << 1)
	65	#define MX2_TSTAT_COMP (1 << 0)
	66
bad3db10	67	/* MX31, MX35, MX25, MX5, MX6 */
38a66f51 AK	68	#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
38a66f51 AK	69	#define V2_TCTL_CLK_IPG (1 << 6)
1f152b48	70	#define V2_TCTL_CLK_PER (2 << 6)
bad3db10	71	#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
38a66f51	72	#define V2_TCTL_FRR (1 << 9)
bad3db10 AH	73	#define V2_TCTL_24MEN (1 << 10)
bad3db10 AH	74	#define V2_TPRER_PRE24M 12
38a66f51 AK	75	#define V2_IR 0x0c
	76	#define V2_TSTAT 0x08
	77	#define V2_TSTAT_OF1 (1 << 0)
	78	#define V2_TCN 0x24
	79	#define V2_TCMP 0x10
d0f349fb	80
bad3db10 AH	81	#define V2_TIMER_RATE_OSC_DIV8 3000000
bad3db10 AH	82
0f3332c4 SH	83	#define timer_is_v1() (cpu_is_mx1() \|\| cpu_is_mx21() \|\| cpu_is_mx27())
	84	#define timer_is_v2() (!timer_is_v1())
	85
d0f349fb JB	86	static struct clock_event_device clockevent_mxc;
	87	static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
	88
6dd74782	89	struct imx_timer {
0931aff7	90	enum imx_gpt_type type;
6dd74782 SG	91	void __iomem *base;
	92	int irq;
	93	struct clk *clk_per;
	94	struct clk *clk_ipg;
9c8694bd SG	95	const struct imx_gpt_data *gpt;
	96	};
	97
	98	struct imx_gpt_data {
	99	void (gpt_setup_tctl)(struct imx_timer imxtm);
6dd74782 SG	100	};
6dd74782 SG	101
ec996ba9	102	static void __iomem *timer_base;
d0f349fb	103
ec996ba9	104	static inline void gpt_irq_disable(void)
d0f349fb	105	{
ec996ba9 SH	106	unsigned int tmp;
ec996ba9 SH	107
0f3332c4	108	if (timer_is_v2())
c7770bba	109	writel_relaxed(0, timer_base + V2_IR);
ec996ba9	110	else {
c7770bba SG	111	tmp = readl_relaxed(timer_base + MXC_TCTL);
c7770bba SG	112	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
ec996ba9 SH	113	}
	114	}
	115
	116	static inline void gpt_irq_enable(void)
	117	{
0f3332c4	118	if (timer_is_v2())
c7770bba	119	writel_relaxed(1<<0, timer_base + V2_IR);
ec996ba9	120	else {
c7770bba	121	writel_relaxed(readl_relaxed(timer_base + MXC_TCTL) \| MX1_2_TCTL_IRQEN,
ec996ba9 SH	122	timer_base + MXC_TCTL);
	123	}
	124	}
	125
	126	static void gpt_irq_acknowledge(void)
	127	{
0f3332c4 SH	128	if (timer_is_v1()) {
0f3332c4 SH	129	if (cpu_is_mx1())
c7770bba	130	writel_relaxed(0, timer_base + MX1_2_TSTAT);
0f3332c4	131	else
c7770bba	132	writel_relaxed(MX2_TSTAT_CAPT \| MX2_TSTAT_COMP,
0f3332c4 SH	133	timer_base + MX1_2_TSTAT);
0f3332c4 SH	134	} else if (timer_is_v2())
c7770bba	135	writel_relaxed(V2_TSTAT_OF1, timer_base + V2_TSTAT);
ec996ba9 SH	136	}
ec996ba9 SH	137
234b6ced	138	static void __iomem *sched_clock_reg;
d0f349fb	139
b93767e3	140	static u64 notrace mxc_read_sched_clock(void)
c124befc	141	{
c7770bba	142	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
c124befc JW	143	}
c124befc JW	144
1119c84a SAS	145	static struct delay_timer imx_delay_timer;
	146
	147	static unsigned long imx_read_current_timer(void)
	148	{
c7770bba	149	return readl_relaxed(sched_clock_reg);
1119c84a SAS	150	}
1119c84a SAS	151
6dd74782	152	static int __init mxc_clocksource_init(struct imx_timer *imxtm)
d0f349fb	153	{
6dd74782 SG	154	unsigned int c = clk_get_rate(imxtm->clk_per);
6dd74782 SG	155	void __iomem *reg = imxtm->base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
d0f349fb	156
1119c84a SAS	157	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	158	imx_delay_timer.freq = c;
	159	register_current_timer_delay(&imx_delay_timer);
	160
234b6ced	161	sched_clock_reg = reg;
ec996ba9	162
b93767e3	163	sched_clock_register(mxc_read_sched_clock, 32, c);
234b6ced RK	164	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
234b6ced RK	165	clocksource_mmio_readl_up);
d0f349fb JB	166	}
	167
	168	/* clock event */
	169
ec996ba9	170	static int mx1_2_set_next_event(unsigned long evt,
d0f349fb JB	171	struct clock_event_device *unused)
	172	{
	173	unsigned long tcmp;
	174
c7770bba	175	tcmp = readl_relaxed(timer_base + MX1_2_TCN) + evt;
d0f349fb	176
c7770bba	177	writel_relaxed(tcmp, timer_base + MX1_2_TCMP);
ec996ba9	178
c7770bba	179	return (int)(tcmp - readl_relaxed(timer_base + MX1_2_TCN)) < 0 ?
ec996ba9 SH	180	-ETIME : 0;
	181	}
	182
38a66f51	183	static int v2_set_next_event(unsigned long evt,
ec996ba9 SH	184	struct clock_event_device *unused)
	185	{
	186	unsigned long tcmp;
	187
c7770bba	188	tcmp = readl_relaxed(timer_base + V2_TCN) + evt;
ec996ba9	189
c7770bba	190	writel_relaxed(tcmp, timer_base + V2_TCMP);
ec996ba9	191
eea8e326	192	return evt < 0x7fffffff &&
c7770bba	193	(int)(tcmp - readl_relaxed(timer_base + V2_TCN)) < 0 ?
d0f349fb JB	194	-ETIME : 0;
	195	}
	196
	197	#ifdef DEBUG
	198	static const char *clock_event_mode_label[] = {
	199	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	200	[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
	201	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
de9c5159 UKK	202	[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
de9c5159 UKK	203	[CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
d0f349fb JB	204	};
	205	#endif /* DEBUG */
	206
	207	static void mxc_set_mode(enum clock_event_mode mode,
	208	struct clock_event_device *evt)
	209	{
	210	unsigned long flags;
	211
	212	/*
	213	* The timer interrupt generation is disabled at least
	214	* for enough time to call mxc_set_next_event()
	215	*/
	216	local_irq_save(flags);
	217
	218	/* Disable interrupt in GPT module */
	219	gpt_irq_disable();
	220
	221	if (mode != clockevent_mode) {
	222	/* Set event time into far-far future */
0f3332c4	223	if (timer_is_v2())
c7770bba	224	writel_relaxed(readl_relaxed(timer_base + V2_TCN) - 3,
38a66f51	225	timer_base + V2_TCMP);
ec996ba9	226	else
c7770bba	227	writel_relaxed(readl_relaxed(timer_base + MX1_2_TCN) - 3,
ec996ba9 SH	228	timer_base + MX1_2_TCMP);
ec996ba9 SH	229
d0f349fb JB	230	/* Clear pending interrupt */
	231	gpt_irq_acknowledge();
	232	}
	233
	234	#ifdef DEBUG
	235	printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
	236	clock_event_mode_label[clockevent_mode],
	237	clock_event_mode_label[mode]);
	238	#endif /* DEBUG */
	239
	240	/* Remember timer mode */
	241	clockevent_mode = mode;
	242	local_irq_restore(flags);
	243
	244	switch (mode) {
	245	case CLOCK_EVT_MODE_PERIODIC:
	246	printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
	247	"supported for i.MX\n");
	248	break;
	249	case CLOCK_EVT_MODE_ONESHOT:
	250	/*
	251	* Do not put overhead of interrupt enable/disable into
	252	* mxc_set_next_event(), the core has about 4 minutes
	253	* to call mxc_set_next_event() or shutdown clock after
	254	* mode switching
	255	*/
	256	local_irq_save(flags);
	257	gpt_irq_enable();
	258	local_irq_restore(flags);
	259	break;
	260	case CLOCK_EVT_MODE_SHUTDOWN:
	261	case CLOCK_EVT_MODE_UNUSED:
	262	case CLOCK_EVT_MODE_RESUME:
	263	/* Left event sources disabled, no more interrupts appear */
	264	break;
	265	}
	266	}
	267
	268	/*
	269	* IRQ handler for the timer
	270	*/
	271	static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
	272	{
	273	struct clock_event_device *evt = &clockevent_mxc;
	274	uint32_t tstat;
	275
0f3332c4	276	if (timer_is_v2())
c7770bba	277	tstat = readl_relaxed(timer_base + V2_TSTAT);
81ec1f92	278	else
c7770bba	279	tstat = readl_relaxed(timer_base + MX1_2_TSTAT);
d0f349fb JB	280
	281	gpt_irq_acknowledge();
	282
	283	evt->event_handler(evt);
	284
	285	return IRQ_HANDLED;
	286	}
	287
	288	static struct irqaction mxc_timer_irq = {
	289	.name = "i.MX Timer Tick",
4c1dd3e5	290	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
d0f349fb JB	291	.handler = mxc_timer_interrupt,
	292	};
	293
	294	static struct clock_event_device clockevent_mxc = {
	295	.name = "mxc_timer1",
	296	.features = CLOCK_EVT_FEAT_ONESHOT,
d0f349fb	297	.set_mode = mxc_set_mode,
ec996ba9	298	.set_next_event = mx1_2_set_next_event,
d0f349fb JB	299	.rating = 200,
	300	};
	301
6dd74782	302	static int __init mxc_clockevent_init(struct imx_timer *imxtm)
d0f349fb	303	{
0f3332c4	304	if (timer_is_v2())
38a66f51	305	clockevent_mxc.set_next_event = v2_set_next_event;
ec996ba9	306
320ab2b0	307	clockevent_mxc.cpumask = cpumask_of(0);
838a2ae8	308	clockevents_config_and_register(&clockevent_mxc,
6dd74782	309	clk_get_rate(imxtm->clk_per),
838a2ae8	310	0xff, 0xfffffffe);
d0f349fb JB	311
	312	return 0;
	313	}
	314
9c8694bd SG	315	static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
	316	{
	317	u32 tctl_val;
	318
	319	tctl_val = MX1_2_TCTL_FRR \| MX1_2_TCTL_CLK_PCLK1 \| MXC_TCTL_TEN;
	320	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	321	}
	322	#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl
	323
	324	static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
	325	{
	326	u32 tctl_val;
	327
	328	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	329	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
	330	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	331	else
	332	tctl_val \|= V2_TCTL_CLK_PER;
	333
	334	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	335	}
	336
	337	static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
d0f349fb	338	{
9c8694bd SG	339	u32 tctl_val;
	340
	341	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	342	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
	343	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	344	/* 24 / 8 = 3 MHz */
	345	writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
	346	tctl_val \|= V2_TCTL_24MEN;
	347	} else {
	348	tctl_val \|= V2_TCTL_CLK_PER;
	349	}
	350
	351	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	352	}
821dc4df	353
9c8694bd SG	354	static const struct imx_gpt_data imx1_gpt_data = {
	355	.gpt_setup_tctl = imx1_gpt_setup_tctl,
	356	};
	357
	358	static const struct imx_gpt_data imx21_gpt_data = {
	359	.gpt_setup_tctl = imx21_gpt_setup_tctl,
	360	};
	361
	362	static const struct imx_gpt_data imx31_gpt_data = {
	363	.gpt_setup_tctl = imx31_gpt_setup_tctl,
	364	};
	365
	366	static const struct imx_gpt_data imx6dl_gpt_data = {
	367	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
	368	};
	369
	370	static void __init _mxc_timer_init(struct imx_timer *imxtm)
	371	{
6dd74782 SG	372	/* Temporary */
	373	timer_base = imxtm->base;
	374
9c8694bd SG	375	switch (imxtm->type) {
	376	case GPT_TYPE_IMX1:
	377	imxtm->gpt = &imx1_gpt_data;
	378	break;
	379	case GPT_TYPE_IMX21:
	380	imxtm->gpt = &imx21_gpt_data;
	381	break;
	382	case GPT_TYPE_IMX31:
	383	imxtm->gpt = &imx31_gpt_data;
	384	break;
	385	case GPT_TYPE_IMX6DL:
	386	imxtm->gpt = &imx6dl_gpt_data;
	387	break;
	388	default:
	389	BUG();
	390	}
	391
6dd74782	392	if (IS_ERR(imxtm->clk_per)) {
2cfb4518 SH	393	pr_err("i.MX timer: unable to get clk\n");
2cfb4518 SH	394	return;
821dc4df	395	}
ec996ba9	396
6dd74782 SG	397	if (!IS_ERR(imxtm->clk_ipg))
6dd74782 SG	398	clk_prepare_enable(imxtm->clk_ipg);
2cfb4518	399
6dd74782	400	clk_prepare_enable(imxtm->clk_per);
d0f349fb JB	401
	402	/*
	403	* Initialise to a known state (all timers off, and timing reset)
	404	*/
d0f349fb	405
6dd74782 SG	406	writel_relaxed(0, imxtm->base + MXC_TCTL);
6dd74782 SG	407	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
ec996ba9	408
9c8694bd	409	imxtm->gpt->gpt_setup_tctl(imxtm);
d0f349fb JB	410
d0f349fb JB	411	/* init and register the timer to the framework */
6dd74782 SG	412	mxc_clocksource_init(imxtm);
6dd74782 SG	413	mxc_clockevent_init(imxtm);
d0f349fb JB	414
d0f349fb JB	415	/* Make irqs happen */
6dd74782	416	setup_irq(imxtm->irq, &mxc_timer_irq);
d0f349fb	417	}
876292d6	418
0931aff7	419	void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
f4696752	420	{
6dd74782 SG	421	struct imx_timer *imxtm;
	422
	423	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	424	BUG_ON(!imxtm);
f4696752	425
6dd74782 SG	426	imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
6dd74782 SG	427	imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
d7f98915	428
6dd74782 SG	429	imxtm->base = ioremap(pbase, SZ_4K);
	430	BUG_ON(!imxtm->base);
	431
0931aff7 SG	432	imxtm->type = type;
0931aff7 SG	433
6dd74782	434	_mxc_timer_init(imxtm);
f4696752 AS	435	}
f4696752 AS	436
bef11c88	437	static void __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
876292d6	438	{
6dd74782 SG	439	struct imx_timer *imxtm;
6dd74782 SG	440	static int initialized;
876292d6	441
6dd74782 SG	442	/* Support one instance only */
6dd74782 SG	443	if (initialized)
fd4959d8 AS	444	return;
fd4959d8 AS	445
6dd74782 SG	446	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
6dd74782 SG	447	BUG_ON(!imxtm);
876292d6	448
6dd74782 SG	449	imxtm->base = of_iomap(np, 0);
	450	WARN_ON(!imxtm->base);
	451	imxtm->irq = irq_of_parse_and_map(np, 0);
	452
	453	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
f4696752	454
bad3db10	455	/* Try osc_per first, and fall back to per otherwise */
6dd74782 SG	456	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	457	if (IS_ERR(imxtm->clk_per))
	458	imxtm->clk_per = of_clk_get_by_name(np, "per");
	459
bef11c88 SG	460	imxtm->type = type;
bef11c88 SG	461
6dd74782	462	_mxc_timer_init(imxtm);
bad3db10	463
6dd74782	464	initialized = 1;
876292d6	465	}
bef11c88 SG	466
	467	static void __init imx1_timer_init_dt(struct device_node *np)
	468	{
	469	mxc_timer_init_dt(np, GPT_TYPE_IMX1);
	470	}
	471
	472	static void __init imx21_timer_init_dt(struct device_node *np)
	473	{
	474	mxc_timer_init_dt(np, GPT_TYPE_IMX21);
	475	}
	476
	477	static void __init imx31_timer_init_dt(struct device_node *np)
	478	{
	479	enum imx_gpt_type type = GPT_TYPE_IMX31;
	480
	481	/*
	482	* We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	483	* GPT device, while they actually have different programming model.
	484	* This is a workaround to keep the existing i.MX6DL/S DTBs continue
	485	* working with the new kernel.
	486	*/
	487	if (of_machine_is_compatible("fsl,imx6dl"))
	488	type = GPT_TYPE_IMX6DL;
	489
	490	mxc_timer_init_dt(np, type);
	491	}
	492
	493	static void __init imx6dl_timer_init_dt(struct device_node *np)
	494	{
	495	mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
	496	}
	497
	498	CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
	499	CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
	500	CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
	501	CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
	502	CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
	503	CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
	504	CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
	505	CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
	506	CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
	507	CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
	508	CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);