[linux-block.git] / arch / arm / mach-imx / time.c

/*
 *  linux/arch/arm/plat-mxc/time.c
 *
 *  Copyright (C) 2000-2001 Deep Blue Solutions
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
 *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/sched_clock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/mach/time.h>

#include "common.h"
#include "hardware.h"

/*
 * There are 2 versions of the timer hardware on Freescale MXC hardware.
 * Version 1: MX1/MXL, MX21, MX27.
 * Version 2: MX25, MX31, MX35, MX37, MX51
 */

/* defines common for all i.MX */
#define MXC_TCTL		0x00
#define MXC_TCTL_TEN		(1 << 0) /* Enable module */
#define MXC_TPRER		0x04

/* MX1, MX21, MX27 */
#define MX1_2_TCTL_CLK_PCLK1	(1 << 1)
#define MX1_2_TCTL_IRQEN	(1 << 4)
#define MX1_2_TCTL_FRR		(1 << 8)
#define MX1_2_TCMP		0x08
#define MX1_2_TCN		0x10
#define MX1_2_TSTAT		0x14

/* MX21, MX27 */
#define MX2_TSTAT_CAPT		(1 << 1)
#define MX2_TSTAT_COMP		(1 << 0)

/* MX31, MX35, MX25, MX5 */
#define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG		(1 << 6)
#define V2_TCTL_CLK_PER		(2 << 6)
#define V2_TCTL_FRR		(1 << 9)
#define V2_IR			0x0c
#define V2_TSTAT		0x08
#define V2_TSTAT_OF1		(1 << 0)
#define V2_TCN			0x24
#define V2_TCMP			0x10

#define timer_is_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
#define timer_is_v2()	(!timer_is_v1())

static struct clock_event_device clockevent_mxc;
static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;

static void __iomem *timer_base;

static inline void gpt_irq_disable(void)
{
	unsigned int tmp;

	if (timer_is_v2())
		__raw_writel(0, timer_base + V2_IR);
	else {
		tmp = __raw_readl(timer_base + MXC_TCTL);
		__raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
	}
}

static inline void gpt_irq_enable(void)
{
	if (timer_is_v2())
		__raw_writel(1<<0, timer_base + V2_IR);
	else {
		__raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
			timer_base + MXC_TCTL);
	}
}

static void gpt_irq_acknowledge(void)
{
	if (timer_is_v1()) {
		if (cpu_is_mx1())
			__raw_writel(0, timer_base + MX1_2_TSTAT);
		else
			__raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
				timer_base + MX1_2_TSTAT);
	} else if (timer_is_v2())
		__raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
}

static void __iomem *sched_clock_reg;

static u64 notrace mxc_read_sched_clock(void)
{
	return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
}

static struct delay_timer imx_delay_timer;

static unsigned long imx_read_current_timer(void)
{
	return __raw_readl(sched_clock_reg);
}

static int __init mxc_clocksource_init(struct clk *timer_clk)
{
	unsigned int c = clk_get_rate(timer_clk);
	void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);

	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	imx_delay_timer.freq = c;
	register_current_timer_delay(&imx_delay_timer);

	sched_clock_reg = reg;

	sched_clock_register(mxc_read_sched_clock, 32, c);
	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
			clocksource_mmio_readl_up);
}

/* clock event */

static int mx1_2_set_next_event(unsigned long evt,
			      struct clock_event_device *unused)
{
	unsigned long tcmp;

	tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;

	__raw_writel(tcmp, timer_base + MX1_2_TCMP);

	return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
				-ETIME : 0;
}

static int v2_set_next_event(unsigned long evt,
			      struct clock_event_device *unused)
{
	unsigned long tcmp;

	tcmp = __raw_readl(timer_base + V2_TCN) + evt;

	__raw_writel(tcmp, timer_base + V2_TCMP);

	return evt < 0x7fffffff &&
		(int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
				-ETIME : 0;
}

#ifdef DEBUG
static const char *clock_event_mode_label[] = {
	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	[CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
	[CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED",
	[CLOCK_EVT_MODE_RESUME]   = "CLOCK_EVT_MODE_RESUME",
};
#endif /* DEBUG */

static void mxc_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	unsigned long flags;

	/*
	 * The timer interrupt generation is disabled at least
	 * for enough time to call mxc_set_next_event()
	 */
	local_irq_save(flags);

	/* Disable interrupt in GPT module */
	gpt_irq_disable();

	if (mode != clockevent_mode) {
		/* Set event time into far-far future */
		if (timer_is_v2())
			__raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
					timer_base + V2_TCMP);
		else
			__raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
					timer_base + MX1_2_TCMP);

		/* Clear pending interrupt */
		gpt_irq_acknowledge();
	}

#ifdef DEBUG
	printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
		clock_event_mode_label[clockevent_mode],
		clock_event_mode_label[mode]);
#endif /* DEBUG */

	/* Remember timer mode */
	clockevent_mode = mode;
	local_irq_restore(flags);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
				"supported for i.MX\n");
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	/*
	 * Do not put overhead of interrupt enable/disable into
	 * mxc_set_next_event(), the core has about 4 minutes
	 * to call mxc_set_next_event() or shutdown clock after
	 * mode switching
	 */
		local_irq_save(flags);
		gpt_irq_enable();
		local_irq_restore(flags);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_RESUME:
		/* Left event sources disabled, no more interrupts appear */
		break;
	}
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_mxc;
	uint32_t tstat;

	if (timer_is_v2())
		tstat = __raw_readl(timer_base + V2_TSTAT);
	else
		tstat = __raw_readl(timer_base + MX1_2_TSTAT);

	gpt_irq_acknowledge();

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mxc_timer_irq = {
	.name		= "i.MX Timer Tick",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= mxc_timer_interrupt,
};

static struct clock_event_device clockevent_mxc = {
	.name		= "mxc_timer1",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= mxc_set_mode,
	.set_next_event	= mx1_2_set_next_event,
	.rating		= 200,
};

static int __init mxc_clockevent_init(struct clk *timer_clk)
{
	if (timer_is_v2())
		clockevent_mxc.set_next_event = v2_set_next_event;

	clockevent_mxc.cpumask = cpumask_of(0);
	clockevents_config_and_register(&clockevent_mxc,
					clk_get_rate(timer_clk),
					0xff, 0xfffffffe);

	return 0;
}

void __init mxc_timer_init(void __iomem *base, int irq)
{
	uint32_t tctl_val;
	struct clk *timer_clk;
	struct clk *timer_ipg_clk;

	timer_clk = clk_get_sys("imx-gpt.0", "per");
	if (IS_ERR(timer_clk)) {
		pr_err("i.MX timer: unable to get clk\n");
		return;
	}

	timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
	if (!IS_ERR(timer_ipg_clk))
		clk_prepare_enable(timer_ipg_clk);

	clk_prepare_enable(timer_clk);

	timer_base = base;

	/*
	 * Initialise to a known state (all timers off, and timing reset)
	 */

	__raw_writel(0, timer_base + MXC_TCTL);
	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */

	if (timer_is_v2())
		tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	else
		tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;

	__raw_writel(tctl_val, timer_base + MXC_TCTL);

	/* init and register the timer to the framework */
	mxc_clocksource_init(timer_clk);
	mxc_clockevent_init(timer_clk);

	/* Make irqs happen */
	setup_irq(irq, &mxc_timer_irq);
}

void __init mxc_timer_init_dt(struct device_node *np)
{
	void __iomem *base;
	int irq;

	base = of_iomap(np, 0);
	WARN_ON(!base);
	irq = irq_of_parse_and_map(np, 0);

	mxc_timer_init(base, irq);
}
Commit	Line	Data
d0f349fb JB	1	/*
	2	* linux/arch/arm/plat-mxc/time.c
	3	*
	4	* Copyright (C) 2000-2001 Deep Blue Solutions
	5	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	6	* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	7	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version 2
	12	* of the License, or (at your option) any later version.
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	21	* MA 02110-1301, USA.
	22	*/
	23
	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
	26	#include <linux/clockchips.h>
	27	#include <linux/clk.h>
1119c84a	28	#include <linux/delay.h>
821dc4df	29	#include <linux/err.h>
38ff87f7	30	#include <linux/sched_clock.h>
876292d6 GC	31	#include <linux/of.h>
	32	#include <linux/of_address.h>
	33	#include <linux/of_irq.h>
d0f349fb	34
d0f349fb	35	#include <asm/mach/time.h>
e3372474 SG	36
e3372474 SG	37	#include "common.h"
50f2de61	38	#include "hardware.h"
ec996ba9	39
0f3332c4 SH	40	/*
	41	* There are 2 versions of the timer hardware on Freescale MXC hardware.
	42	* Version 1: MX1/MXL, MX21, MX27.
	43	* Version 2: MX25, MX31, MX35, MX37, MX51
	44	*/
	45
ec996ba9 SH	46	/* defines common for all i.MX */
ec996ba9 SH	47	#define MXC_TCTL 0x00
0f3332c4	48	#define MXC_TCTL_TEN (1 << 0) /* Enable module */
ec996ba9 SH	49	#define MXC_TPRER 0x04
	50
	51	/* MX1, MX21, MX27 */
	52	#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
	53	#define MX1_2_TCTL_IRQEN (1 << 4)
	54	#define MX1_2_TCTL_FRR (1 << 8)
	55	#define MX1_2_TCMP 0x08
	56	#define MX1_2_TCN 0x10
	57	#define MX1_2_TSTAT 0x14
	58
	59	/* MX21, MX27 */
	60	#define MX2_TSTAT_CAPT (1 << 1)
	61	#define MX2_TSTAT_COMP (1 << 0)
	62
13cf8df9	63	/* MX31, MX35, MX25, MX5 */
38a66f51 AK	64	#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
38a66f51 AK	65	#define V2_TCTL_CLK_IPG (1 << 6)
1f152b48	66	#define V2_TCTL_CLK_PER (2 << 6)
38a66f51 AK	67	#define V2_TCTL_FRR (1 << 9)
	68	#define V2_IR 0x0c
	69	#define V2_TSTAT 0x08
	70	#define V2_TSTAT_OF1 (1 << 0)
	71	#define V2_TCN 0x24
	72	#define V2_TCMP 0x10
d0f349fb	73
0f3332c4 SH	74	#define timer_is_v1() (cpu_is_mx1() \|\| cpu_is_mx21() \|\| cpu_is_mx27())
	75	#define timer_is_v2() (!timer_is_v1())
	76
d0f349fb JB	77	static struct clock_event_device clockevent_mxc;
	78	static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
	79
ec996ba9	80	static void __iomem *timer_base;
d0f349fb	81
ec996ba9	82	static inline void gpt_irq_disable(void)
d0f349fb	83	{
ec996ba9 SH	84	unsigned int tmp;
ec996ba9 SH	85
0f3332c4	86	if (timer_is_v2())
38a66f51	87	__raw_writel(0, timer_base + V2_IR);
ec996ba9 SH	88	else {
	89	tmp = __raw_readl(timer_base + MXC_TCTL);
	90	__raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
	91	}
	92	}
	93
	94	static inline void gpt_irq_enable(void)
	95	{
0f3332c4	96	if (timer_is_v2())
38a66f51	97	__raw_writel(1<<0, timer_base + V2_IR);
ec996ba9 SH	98	else {
	99	__raw_writel(__raw_readl(timer_base + MXC_TCTL) \| MX1_2_TCTL_IRQEN,
	100	timer_base + MXC_TCTL);
	101	}
	102	}
	103
	104	static void gpt_irq_acknowledge(void)
	105	{
0f3332c4 SH	106	if (timer_is_v1()) {
	107	if (cpu_is_mx1())
	108	__raw_writel(0, timer_base + MX1_2_TSTAT);
	109	else
	110	__raw_writel(MX2_TSTAT_CAPT \| MX2_TSTAT_COMP,
	111	timer_base + MX1_2_TSTAT);
	112	} else if (timer_is_v2())
d943f2c8	113	__raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
ec996ba9 SH	114	}
ec996ba9 SH	115
234b6ced	116	static void __iomem *sched_clock_reg;
d0f349fb	117
b93767e3	118	static u64 notrace mxc_read_sched_clock(void)
c124befc	119	{
2f0778af	120	return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
c124befc JW	121	}
c124befc JW	122
1119c84a SAS	123	static struct delay_timer imx_delay_timer;
	124
	125	static unsigned long imx_read_current_timer(void)
	126	{
	127	return __raw_readl(sched_clock_reg);
	128	}
	129
30c730f8	130	static int __init mxc_clocksource_init(struct clk *timer_clk)
d0f349fb	131	{
058b7a6f	132	unsigned int c = clk_get_rate(timer_clk);
234b6ced	133	void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
d0f349fb	134
1119c84a SAS	135	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	136	imx_delay_timer.freq = c;
	137	register_current_timer_delay(&imx_delay_timer);
	138
234b6ced	139	sched_clock_reg = reg;
ec996ba9	140
b93767e3	141	sched_clock_register(mxc_read_sched_clock, 32, c);
234b6ced RK	142	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
234b6ced RK	143	clocksource_mmio_readl_up);
d0f349fb JB	144	}
	145
	146	/* clock event */
	147
ec996ba9	148	static int mx1_2_set_next_event(unsigned long evt,
d0f349fb JB	149	struct clock_event_device *unused)
	150	{
	151	unsigned long tcmp;
	152
ec996ba9	153	tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
d0f349fb	154
ec996ba9 SH	155	__raw_writel(tcmp, timer_base + MX1_2_TCMP);
	156
	157	return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
	158	-ETIME : 0;
	159	}
	160
38a66f51	161	static int v2_set_next_event(unsigned long evt,
ec996ba9 SH	162	struct clock_event_device *unused)
	163	{
	164	unsigned long tcmp;
	165
38a66f51	166	tcmp = __raw_readl(timer_base + V2_TCN) + evt;
ec996ba9	167
38a66f51	168	__raw_writel(tcmp, timer_base + V2_TCMP);
ec996ba9	169
eea8e326 SG	170	return evt < 0x7fffffff &&
eea8e326 SG	171	(int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
d0f349fb JB	172	-ETIME : 0;
	173	}
	174
	175	#ifdef DEBUG
	176	static const char *clock_event_mode_label[] = {
	177	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	178	[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
	179	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
de9c5159 UKK	180	[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
de9c5159 UKK	181	[CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
d0f349fb JB	182	};
	183	#endif /* DEBUG */
	184
	185	static void mxc_set_mode(enum clock_event_mode mode,
	186	struct clock_event_device *evt)
	187	{
	188	unsigned long flags;
	189
	190	/*
	191	* The timer interrupt generation is disabled at least
	192	* for enough time to call mxc_set_next_event()
	193	*/
	194	local_irq_save(flags);
	195
	196	/* Disable interrupt in GPT module */
	197	gpt_irq_disable();
	198
	199	if (mode != clockevent_mode) {
	200	/* Set event time into far-far future */
0f3332c4	201	if (timer_is_v2())
38a66f51 AK	202	__raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
38a66f51 AK	203	timer_base + V2_TCMP);
ec996ba9 SH	204	else
	205	__raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
	206	timer_base + MX1_2_TCMP);
	207
d0f349fb JB	208	/* Clear pending interrupt */
	209	gpt_irq_acknowledge();
	210	}
	211
	212	#ifdef DEBUG
	213	printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
	214	clock_event_mode_label[clockevent_mode],
	215	clock_event_mode_label[mode]);
	216	#endif /* DEBUG */
	217
	218	/* Remember timer mode */
	219	clockevent_mode = mode;
	220	local_irq_restore(flags);
	221
	222	switch (mode) {
	223	case CLOCK_EVT_MODE_PERIODIC:
	224	printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
	225	"supported for i.MX\n");
	226	break;
	227	case CLOCK_EVT_MODE_ONESHOT:
	228	/*
	229	* Do not put overhead of interrupt enable/disable into
	230	* mxc_set_next_event(), the core has about 4 minutes
	231	* to call mxc_set_next_event() or shutdown clock after
	232	* mode switching
	233	*/
	234	local_irq_save(flags);
	235	gpt_irq_enable();
	236	local_irq_restore(flags);
	237	break;
	238	case CLOCK_EVT_MODE_SHUTDOWN:
	239	case CLOCK_EVT_MODE_UNUSED:
	240	case CLOCK_EVT_MODE_RESUME:
	241	/* Left event sources disabled, no more interrupts appear */
	242	break;
	243	}
	244	}
	245
	246	/*
	247	* IRQ handler for the timer
	248	*/
	249	static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
	250	{
	251	struct clock_event_device *evt = &clockevent_mxc;
	252	uint32_t tstat;
	253
0f3332c4	254	if (timer_is_v2())
38a66f51	255	tstat = __raw_readl(timer_base + V2_TSTAT);
81ec1f92 SH	256	else
81ec1f92 SH	257	tstat = __raw_readl(timer_base + MX1_2_TSTAT);
d0f349fb JB	258
	259	gpt_irq_acknowledge();
	260
	261	evt->event_handler(evt);
	262
	263	return IRQ_HANDLED;
	264	}
	265
	266	static struct irqaction mxc_timer_irq = {
	267	.name = "i.MX Timer Tick",
4c1dd3e5	268	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
d0f349fb JB	269	.handler = mxc_timer_interrupt,
	270	};
	271
	272	static struct clock_event_device clockevent_mxc = {
	273	.name = "mxc_timer1",
	274	.features = CLOCK_EVT_FEAT_ONESHOT,
d0f349fb	275	.set_mode = mxc_set_mode,
ec996ba9	276	.set_next_event = mx1_2_set_next_event,
d0f349fb JB	277	.rating = 200,
	278	};
	279
30c730f8	280	static int __init mxc_clockevent_init(struct clk *timer_clk)
d0f349fb	281	{
0f3332c4	282	if (timer_is_v2())
38a66f51	283	clockevent_mxc.set_next_event = v2_set_next_event;
ec996ba9	284
320ab2b0	285	clockevent_mxc.cpumask = cpumask_of(0);
838a2ae8 SG	286	clockevents_config_and_register(&clockevent_mxc,
	287	clk_get_rate(timer_clk),
	288	0xff, 0xfffffffe);
d0f349fb JB	289
	290	return 0;
	291	}
	292
2cfb4518	293	void __init mxc_timer_init(void __iomem *base, int irq)
d0f349fb	294	{
ec996ba9	295	uint32_t tctl_val;
2cfb4518	296	struct clk *timer_clk;
821dc4df SH	297	struct clk *timer_ipg_clk;
821dc4df SH	298
2cfb4518 SH	299	timer_clk = clk_get_sys("imx-gpt.0", "per");
	300	if (IS_ERR(timer_clk)) {
	301	pr_err("i.MX timer: unable to get clk\n");
	302	return;
821dc4df	303	}
ec996ba9	304
2cfb4518 SH	305	timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
	306	if (!IS_ERR(timer_ipg_clk))
	307	clk_prepare_enable(timer_ipg_clk);
	308
46f417de	309	clk_prepare_enable(timer_clk);
d0f349fb	310
8db5d1a6	311	timer_base = base;
ec996ba9	312
d0f349fb JB	313	/*
	314	* Initialise to a known state (all timers off, and timing reset)
	315	*/
d0f349fb	316
ec996ba9 SH	317	__raw_writel(0, timer_base + MXC_TCTL);
	318	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
	319
0f3332c4	320	if (timer_is_v2())
1f152b48	321	tctl_val = V2_TCTL_CLK_PER \| V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
ec996ba9 SH	322	else
	323	tctl_val = MX1_2_TCTL_FRR \| MX1_2_TCTL_CLK_PCLK1 \| MXC_TCTL_TEN;
	324
	325	__raw_writel(tctl_val, timer_base + MXC_TCTL);
d0f349fb JB	326
d0f349fb JB	327	/* init and register the timer to the framework */
30c730f8 SH	328	mxc_clocksource_init(timer_clk);
30c730f8 SH	329	mxc_clockevent_init(timer_clk);
d0f349fb JB	330
d0f349fb JB	331	/* Make irqs happen */
ec996ba9	332	setup_irq(irq, &mxc_timer_irq);
d0f349fb	333	}
876292d6 GC	334
	335	void __init mxc_timer_init_dt(struct device_node *np)
	336	{
	337	void __iomem *base;
	338	int irq;
	339
	340	base = of_iomap(np, 0);
	341	WARN_ON(!base);
	342	irq = irq_of_parse_and_map(np, 0);
	343
	344	mxc_timer_init(base, irq);
	345	}