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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
eea643f7 JB |
2 | /* |
3 | * Copyright (C) 1999 ARM Limited | |
4 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
5 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
6 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
74bef9a4 | 7 | * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com |
eea643f7 JB |
8 | */ |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/io.h> | |
74bef9a4 IY |
13 | #include <linux/err.h> |
14 | #include <linux/delay.h> | |
c1e31d12 SG |
15 | #include <linux/of.h> |
16 | #include <linux/of_address.h> | |
eea643f7 | 17 | |
9f97da78 | 18 | #include <asm/system_misc.h> |
eea643f7 | 19 | #include <asm/proc-fns.h> |
c2932bf4 | 20 | #include <asm/mach-types.h> |
e6a07569 | 21 | #include <asm/hardware/cache-l2x0.h> |
eea643f7 | 22 | |
e3372474 | 23 | #include "common.h" |
50f2de61 | 24 | #include "hardware.h" |
e3372474 | 25 | |
be124c94 | 26 | static void __iomem *wdog_base; |
18cb680f | 27 | static struct clk *wdog_clk; |
6f98cb22 | 28 | static int wcr_enable = (1 << 2); |
eea643f7 JB |
29 | |
30 | /* | |
31 | * Reset the system. It is called by machine_restart(). | |
32 | */ | |
7b6d864b | 33 | void mxc_restart(enum reboot_mode mode, const char *cmd) |
eea643f7 | 34 | { |
5a6e1502 AS |
35 | if (!wdog_base) |
36 | goto reset_fallback; | |
37 | ||
ce8ad883 | 38 | if (!IS_ERR(wdog_clk)) |
18cb680f | 39 | clk_enable(wdog_clk); |
eea643f7 | 40 | |
eea643f7 | 41 | /* Assert SRS signal */ |
c553138f | 42 | imx_writew(wcr_enable, wdog_base); |
2c11b57a SG |
43 | /* |
44 | * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be | |
45 | * written twice), we add another two writes to ensure there must be at | |
46 | * least two writes happen in the same one 32kHz clock period. We save | |
47 | * the target check here, since the writes shouldn't be a huge burden | |
48 | * for other platforms. | |
49 | */ | |
c553138f JB |
50 | imx_writew(wcr_enable, wdog_base); |
51 | imx_writew(wcr_enable, wdog_base); | |
74bef9a4 IY |
52 | |
53 | /* wait for reset to assert... */ | |
54 | mdelay(500); | |
55 | ||
18cb680f | 56 | pr_err("%s: Watchdog reset failed to assert reset\n", __func__); |
74bef9a4 IY |
57 | |
58 | /* delay to allow the serial port to show the message */ | |
59 | mdelay(50); | |
60 | ||
5a6e1502 | 61 | reset_fallback: |
74bef9a4 | 62 | /* we'll take a jump through zero as a poor second */ |
e879c862 | 63 | soft_restart(0); |
eea643f7 | 64 | } |
be124c94 | 65 | |
18cb680f | 66 | void __init mxc_arch_reset_init(void __iomem *base) |
be124c94 SH |
67 | { |
68 | wdog_base = base; | |
18cb680f SG |
69 | |
70 | wdog_clk = clk_get_sys("imx2-wdt.0", NULL); | |
ce8ad883 | 71 | if (IS_ERR(wdog_clk)) |
18cb680f | 72 | pr_warn("%s: failed to get wdog clock\n", __func__); |
ce8ad883 AS |
73 | else |
74 | clk_prepare(wdog_clk); | |
be124c94 | 75 | } |
c1e31d12 | 76 | |
6f98cb22 AB |
77 | #ifdef CONFIG_SOC_IMX1 |
78 | void __init imx1_reset_init(void __iomem *base) | |
79 | { | |
80 | wcr_enable = (1 << 0); | |
81 | mxc_arch_reset_init(base); | |
82 | } | |
83 | #endif | |
84 | ||
e6a07569 | 85 | #ifdef CONFIG_CACHE_L2X0 |
10eff770 | 86 | void __init imx_init_l2cache(void) |
e6a07569 SG |
87 | { |
88 | void __iomem *l2x0_base; | |
89 | struct device_node *np; | |
90 | unsigned int val; | |
91 | ||
92 | np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); | |
93 | if (!np) | |
510aca64 | 94 | return; |
e6a07569 SG |
95 | |
96 | l2x0_base = of_iomap(np, 0); | |
510aca64 AS |
97 | if (!l2x0_base) |
98 | goto put_node; | |
e6a07569 | 99 | |
c00e4c54 AS |
100 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { |
101 | /* Configure the L2 PREFETCH and POWER registers */ | |
102 | val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); | |
b8290371 AS |
103 | val |= L310_PREFETCH_CTRL_DBL_LINEFILL | |
104 | L310_PREFETCH_CTRL_INSTR_PREFETCH | | |
1d9e9477 AS |
105 | L310_PREFETCH_CTRL_DATA_PREFETCH; |
106 | ||
107 | /* Set perfetch offset to improve performance */ | |
108 | val &= ~L310_PREFETCH_CTRL_OFFSET_MASK; | |
109 | val |= 15; | |
110 | ||
c00e4c54 AS |
111 | writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); |
112 | } | |
e6a07569 SG |
113 | |
114 | iounmap(l2x0_base); | |
510aca64 | 115 | put_node: |
e6a07569 | 116 | of_node_put(np); |
e6a07569 SG |
117 | } |
118 | #endif |