Commit | Line | Data |
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eea643f7 JB |
1 | /* |
2 | * Copyright (C) 1999 ARM Limited | |
3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
74bef9a4 | 6 | * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com |
eea643f7 JB |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
eea643f7 JB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/io.h> | |
74bef9a4 IY |
22 | #include <linux/err.h> |
23 | #include <linux/delay.h> | |
c1e31d12 SG |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
eea643f7 | 26 | |
9f97da78 | 27 | #include <asm/system_misc.h> |
eea643f7 | 28 | #include <asm/proc-fns.h> |
c2932bf4 | 29 | #include <asm/mach-types.h> |
e6a07569 | 30 | #include <asm/hardware/cache-l2x0.h> |
eea643f7 | 31 | |
e3372474 | 32 | #include "common.h" |
50f2de61 | 33 | #include "hardware.h" |
e3372474 | 34 | |
be124c94 | 35 | static void __iomem *wdog_base; |
18cb680f | 36 | static struct clk *wdog_clk; |
eea643f7 JB |
37 | |
38 | /* | |
39 | * Reset the system. It is called by machine_restart(). | |
40 | */ | |
7b6d864b | 41 | void mxc_restart(enum reboot_mode mode, const char *cmd) |
eea643f7 | 42 | { |
be124c94 SH |
43 | unsigned int wcr_enable; |
44 | ||
5a6e1502 AS |
45 | if (!wdog_base) |
46 | goto reset_fallback; | |
47 | ||
ce8ad883 | 48 | if (!IS_ERR(wdog_clk)) |
18cb680f | 49 | clk_enable(wdog_clk); |
eea643f7 | 50 | |
18cb680f SG |
51 | if (cpu_is_mx1()) |
52 | wcr_enable = (1 << 0); | |
53 | else | |
be124c94 | 54 | wcr_enable = (1 << 2); |
eea643f7 | 55 | |
eea643f7 | 56 | /* Assert SRS signal */ |
be124c94 | 57 | __raw_writew(wcr_enable, wdog_base); |
2c11b57a SG |
58 | /* |
59 | * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be | |
60 | * written twice), we add another two writes to ensure there must be at | |
61 | * least two writes happen in the same one 32kHz clock period. We save | |
62 | * the target check here, since the writes shouldn't be a huge burden | |
63 | * for other platforms. | |
64 | */ | |
65 | __raw_writew(wcr_enable, wdog_base); | |
87a84b69 | 66 | __raw_writew(wcr_enable, wdog_base); |
74bef9a4 IY |
67 | |
68 | /* wait for reset to assert... */ | |
69 | mdelay(500); | |
70 | ||
18cb680f | 71 | pr_err("%s: Watchdog reset failed to assert reset\n", __func__); |
74bef9a4 IY |
72 | |
73 | /* delay to allow the serial port to show the message */ | |
74 | mdelay(50); | |
75 | ||
5a6e1502 | 76 | reset_fallback: |
74bef9a4 | 77 | /* we'll take a jump through zero as a poor second */ |
e879c862 | 78 | soft_restart(0); |
eea643f7 | 79 | } |
be124c94 | 80 | |
18cb680f | 81 | void __init mxc_arch_reset_init(void __iomem *base) |
be124c94 SH |
82 | { |
83 | wdog_base = base; | |
18cb680f SG |
84 | |
85 | wdog_clk = clk_get_sys("imx2-wdt.0", NULL); | |
ce8ad883 | 86 | if (IS_ERR(wdog_clk)) |
18cb680f | 87 | pr_warn("%s: failed to get wdog clock\n", __func__); |
ce8ad883 AS |
88 | else |
89 | clk_prepare(wdog_clk); | |
be124c94 | 90 | } |
c1e31d12 | 91 | |
e6a07569 | 92 | #ifdef CONFIG_CACHE_L2X0 |
10eff770 | 93 | void __init imx_init_l2cache(void) |
e6a07569 SG |
94 | { |
95 | void __iomem *l2x0_base; | |
96 | struct device_node *np; | |
97 | unsigned int val; | |
98 | ||
99 | np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); | |
100 | if (!np) | |
101 | goto out; | |
102 | ||
103 | l2x0_base = of_iomap(np, 0); | |
104 | if (!l2x0_base) { | |
105 | of_node_put(np); | |
106 | goto out; | |
107 | } | |
108 | ||
109 | /* Configure the L2 PREFETCH and POWER registers */ | |
1a5a954c | 110 | val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); |
e6a07569 | 111 | val |= 0x70800000; |
9779f0e1 JL |
112 | /* |
113 | * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 | |
114 | * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 | |
115 | * But according to ARM PL310 errata: 752271 | |
116 | * ID: 752271: Double linefill feature can cause data corruption | |
117 | * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 | |
118 | * Workaround: The only workaround to this erratum is to disable the | |
119 | * double linefill feature. This is the default behavior. | |
120 | */ | |
121 | if (cpu_is_imx6q()) | |
122 | val &= ~(1 << 30 | 1 << 23); | |
1a5a954c | 123 | writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); |
e6a07569 SG |
124 | |
125 | iounmap(l2x0_base); | |
126 | of_node_put(np); | |
127 | ||
128 | out: | |
d453ef75 | 129 | l2x0_of_init(0, ~0); |
e6a07569 SG |
130 | } |
131 | #endif |