[linux-2.6-block.git] / arch / arm / mach-imx / pm-imx7ulp.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2018 NXP
 *   Author: Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include "common.h"

#define SMC_PMCTRL		0x10
#define BP_PMCTRL_PSTOPO        16
#define PSTOPO_PSTOP3		0x3
#define PSTOPO_PSTOP2		0x2
#define PSTOPO_PSTOP1		0x1
#define BP_PMCTRL_RUNM		8
#define RUNM_RUN		0
#define BP_PMCTRL_STOPM		0
#define STOPM_STOP		0

#define BM_PMCTRL_PSTOPO	(3 << BP_PMCTRL_PSTOPO)
#define BM_PMCTRL_RUNM		(3 << BP_PMCTRL_RUNM)
#define BM_PMCTRL_STOPM		(7 << BP_PMCTRL_STOPM)

static void __iomem *smc1_base;

int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode)
{
	u32 val = readl_relaxed(smc1_base + SMC_PMCTRL);

	/* clear all */
	val &= ~(BM_PMCTRL_RUNM | BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO);

	switch (mode) {
	case ULP_PM_RUN:
		/* system/bus clock enabled */
		val |= PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO;
		break;
	case ULP_PM_WAIT:
		/* system clock disabled, bus clock enabled */
		val |= PSTOPO_PSTOP2 << BP_PMCTRL_PSTOPO;
		break;
	case ULP_PM_STOP:
		/* system/bus clock disabled */
		val |= PSTOPO_PSTOP1 << BP_PMCTRL_PSTOPO;
		break;
	default:
		return -EINVAL;
	}

	writel_relaxed(val, smc1_base + SMC_PMCTRL);

	return 0;
}

void __init imx7ulp_pm_init(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
	smc1_base = of_iomap(np, 0);
	WARN_ON(!smc1_base);

	imx7ulp_set_lpm(ULP_PM_RUN);
}
Commit	Line	Data
de70d0e9 D	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2016 Freescale Semiconductor, Inc.
	4	* Copyright 2017-2018 NXP
	5	* Author: Dong Aisheng <aisheng.dong@nxp.com>
	6	*/
	7
	8	#include <linux/io.h>
	9	#include <linux/of.h>
	10	#include <linux/of_address.h>
	11
6d45a402 AH	12	#include "common.h"
6d45a402 AH	13
de70d0e9 D	14	#define SMC_PMCTRL 0x10
	15	#define BP_PMCTRL_PSTOPO 16
	16	#define PSTOPO_PSTOP3 0x3
6d45a402 AH	17	#define PSTOPO_PSTOP2 0x2
	18	#define PSTOPO_PSTOP1 0x1
	19	#define BP_PMCTRL_RUNM 8
	20	#define RUNM_RUN 0
	21	#define BP_PMCTRL_STOPM 0
	22	#define STOPM_STOP 0
	23
	24	#define BM_PMCTRL_PSTOPO (3 << BP_PMCTRL_PSTOPO)
	25	#define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM)
	26	#define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM)
	27
	28	static void __iomem *smc1_base;
	29
	30	int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode)
	31	{
	32	u32 val = readl_relaxed(smc1_base + SMC_PMCTRL);
	33
	34	/* clear all */
	35	val &= ~(BM_PMCTRL_RUNM \| BM_PMCTRL_STOPM \| BM_PMCTRL_PSTOPO);
	36
	37	switch (mode) {
	38	case ULP_PM_RUN:
	39	/* system/bus clock enabled */
	40	val \|= PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO;
	41	break;
	42	case ULP_PM_WAIT:
	43	/* system clock disabled, bus clock enabled */
	44	val \|= PSTOPO_PSTOP2 << BP_PMCTRL_PSTOPO;
	45	break;
	46	case ULP_PM_STOP:
	47	/* system/bus clock disabled */
	48	val \|= PSTOPO_PSTOP1 << BP_PMCTRL_PSTOPO;
	49	break;
	50	default:
	51	return -EINVAL;
	52	}
	53
	54	writel_relaxed(val, smc1_base + SMC_PMCTRL);
	55
	56	return 0;
	57	}
de70d0e9 D	58
	59	void __init imx7ulp_pm_init(void)
	60	{
	61	struct device_node *np;
de70d0e9 D	62
	63	np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
	64	smc1_base = of_iomap(np, 0);
	65	WARN_ON(!smc1_base);
	66
6d45a402	67	imx7ulp_set_lpm(ULP_PM_RUN);
de70d0e9	68	}