Commit | Line | Data |
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0adf882b | 1 | /* |
784a90c0 SH |
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
3 | * | |
0adf882b DN |
4 | * The code contained herein is licensed under the GNU General Public |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
784a90c0 SH |
11 | #include <linux/suspend.h> |
12 | #include <linux/clk.h> | |
0adf882b | 13 | #include <linux/io.h> |
784a90c0 SH |
14 | #include <linux/err.h> |
15 | #include <asm/cacheflush.h> | |
16 | #include <asm/tlbflush.h> | |
41e7daf2 | 17 | #include <mach/common.h> |
784a90c0 SH |
18 | #include <mach/hardware.h> |
19 | #include "crm-regs-imx5.h" | |
20 | ||
21 | static struct clk *gpc_dvfs_clk; | |
0adf882b | 22 | |
784a90c0 SH |
23 | /* |
24 | * set cpu low power mode before WFI instruction. This function is called | |
25 | * mx5 because it can be used for mx50, mx51, and mx53. | |
26 | */ | |
0adf882b DN |
27 | void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) |
28 | { | |
29 | u32 plat_lpc, arm_srpgcr, ccm_clpcr; | |
30 | u32 empgc0, empgc1; | |
31 | int stop_mode = 0; | |
32 | ||
33 | /* always allow platform to issue a deep sleep mode request */ | |
34 | plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & | |
35 | ~(MXC_CORTEXA8_PLAT_LPC_DSM); | |
36 | ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); | |
37 | arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); | |
38 | empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); | |
39 | empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); | |
40 | ||
41 | switch (mode) { | |
42 | case WAIT_CLOCKED: | |
43 | break; | |
44 | case WAIT_UNCLOCKED: | |
45 | ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; | |
46 | break; | |
47 | case WAIT_UNCLOCKED_POWER_OFF: | |
48 | case STOP_POWER_OFF: | |
49 | plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM | |
50 | | MXC_CORTEXA8_PLAT_LPC_DBG_DSM; | |
51 | if (mode == WAIT_UNCLOCKED_POWER_OFF) { | |
52 | ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; | |
53 | ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; | |
54 | ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; | |
55 | stop_mode = 0; | |
56 | } else { | |
57 | ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; | |
58 | ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; | |
59 | ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; | |
60 | ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; | |
61 | stop_mode = 1; | |
62 | } | |
63 | arm_srpgcr |= MXC_SRPGCR_PCR; | |
0adf882b DN |
64 | break; |
65 | case STOP_POWER_ON: | |
66 | ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; | |
67 | break; | |
68 | default: | |
69 | printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); | |
70 | return; | |
71 | } | |
72 | ||
73 | __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); | |
74 | __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); | |
75 | __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); | |
76 | ||
77 | /* Enable NEON SRPG for all but MX50TO1.0. */ | |
78 | if (mx50_revision() != IMX_CHIP_REVISION_1_0) | |
79 | __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); | |
80 | ||
81 | if (stop_mode) { | |
82 | empgc0 |= MXC_SRPGCR_PCR; | |
83 | empgc1 |= MXC_SRPGCR_PCR; | |
84 | ||
85 | __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); | |
86 | __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); | |
87 | } | |
88 | } | |
784a90c0 SH |
89 | |
90 | static int mx5_suspend_prepare(void) | |
91 | { | |
d816c6e6 | 92 | return clk_prepare_enable(gpc_dvfs_clk); |
784a90c0 SH |
93 | } |
94 | ||
95 | static int mx5_suspend_enter(suspend_state_t state) | |
96 | { | |
97 | switch (state) { | |
98 | case PM_SUSPEND_MEM: | |
99 | mx5_cpu_lp_set(STOP_POWER_OFF); | |
100 | break; | |
101 | case PM_SUSPEND_STANDBY: | |
102 | mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); | |
103 | break; | |
104 | default: | |
105 | return -EINVAL; | |
106 | } | |
107 | ||
108 | if (state == PM_SUSPEND_MEM) { | |
109 | local_flush_tlb_all(); | |
110 | flush_cache_all(); | |
111 | ||
112 | /*clear the EMPGC0/1 bits */ | |
113 | __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); | |
114 | __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); | |
115 | } | |
116 | cpu_do_idle(); | |
117 | return 0; | |
118 | } | |
119 | ||
120 | static void mx5_suspend_finish(void) | |
121 | { | |
d816c6e6 | 122 | clk_disable_unprepare(gpc_dvfs_clk); |
784a90c0 SH |
123 | } |
124 | ||
125 | static int mx5_pm_valid(suspend_state_t state) | |
126 | { | |
127 | return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); | |
128 | } | |
129 | ||
130 | static const struct platform_suspend_ops mx5_suspend_ops = { | |
131 | .valid = mx5_pm_valid, | |
132 | .prepare = mx5_suspend_prepare, | |
133 | .enter = mx5_suspend_enter, | |
134 | .finish = mx5_suspend_finish, | |
135 | }; | |
136 | ||
137 | static int __init mx5_pm_init(void) | |
138 | { | |
139 | if (!cpu_is_mx51() && !cpu_is_mx53()) | |
140 | return 0; | |
141 | ||
142 | if (gpc_dvfs_clk == NULL) | |
143 | gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); | |
144 | ||
145 | if (!IS_ERR(gpc_dvfs_clk)) { | |
146 | if (cpu_is_mx51()) | |
147 | suspend_set_ops(&mx5_suspend_ops); | |
148 | } else | |
149 | return -EPERM; | |
150 | ||
151 | return 0; | |
152 | } | |
153 | device_initcall(mx5_pm_init); |