[linux-2.6-block.git] / arch / arm / mach-imx / mxc.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright 2004-2007, 2010-2015 Freescale Semiconductor, Inc.
 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 */

#ifndef __ASM_ARCH_MXC_H__
#define __ASM_ARCH_MXC_H__

#include <linux/types.h>

#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif

#define MXC_CPU_MX1		1
#define MXC_CPU_MX21		21
#define MXC_CPU_MX25		25
#define MXC_CPU_MX27		27
#define MXC_CPU_MX31		31
#define MXC_CPU_MX35		35
#define MXC_CPU_MX51		51
#define MXC_CPU_MX53		53
#define MXC_CPU_IMX6SL		0x60
#define MXC_CPU_IMX6DL		0x61
#define MXC_CPU_IMX6SX		0x62
#define MXC_CPU_IMX6Q		0x63
#define MXC_CPU_IMX6UL		0x64
#define MXC_CPU_IMX6ULL		0x65
/* virtual cpu id for i.mx6ulz */
#define MXC_CPU_IMX6ULZ		0x6b
#define MXC_CPU_IMX6SLL		0x67
#define MXC_CPU_IMX7D		0x72
#define MXC_CPU_IMX7ULP		0xff

#define IMX_DDR_TYPE_LPDDR2		1

#ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type;

#ifdef CONFIG_SOC_IMX6SL
static inline bool cpu_is_imx6sl(void)
{
	return __mxc_cpu_type == MXC_CPU_IMX6SL;
}
#else
static inline bool cpu_is_imx6sl(void)
{
	return false;
}
#endif

static inline bool cpu_is_imx6dl(void)
{
	return __mxc_cpu_type == MXC_CPU_IMX6DL;
}

static inline bool cpu_is_imx6sx(void)
{
	return __mxc_cpu_type == MXC_CPU_IMX6SX;
}

static inline bool cpu_is_imx6ul(void)
{
	return __mxc_cpu_type == MXC_CPU_IMX6UL;
}

static inline bool cpu_is_imx6ull(void)
{
	return __mxc_cpu_type == MXC_CPU_IMX6ULL;
}

static inline bool cpu_is_imx6ulz(void)
{
	return __mxc_cpu_type == MXC_CPU_IMX6ULZ;
}

static inline bool cpu_is_imx6sll(void)
{
	return __mxc_cpu_type == MXC_CPU_IMX6SLL;
}

static inline bool cpu_is_imx6q(void)
{
	return __mxc_cpu_type == MXC_CPU_IMX6Q;
}

static inline bool cpu_is_imx7d(void)
{
	return __mxc_cpu_type == MXC_CPU_IMX7D;
}

struct cpu_op {
	u32 cpu_rate;
};

int tzic_enable_wake(void);

extern struct cpu_op *(*get_cpu_op)(int *op);
#endif

#define imx_readl	readl_relaxed
#define imx_readw	readw_relaxed
#define imx_writel	writel_relaxed
#define imx_writew	writew_relaxed

#endif /*  __ASM_ARCH_MXC_H__ */
Commit	Line	Data
16216333	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
52c543f9	2	/*
5739b919	3	* Copyright 2004-2007, 2010-2015 Freescale Semiconductor, Inc.
d0f349fb	4	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
52c543f9 QJ	5	*/
	6
	7	#ifndef __ASM_ARCH_MXC_H__
	8	#define __ASM_ARCH_MXC_H__
	9
64f102b6 YS	10	#include <linux/types.h>
64f102b6 YS	11
52c543f9 QJ	12	#ifndef __ASM_ARCH_MXC_HARDWARE_H__
	13	#error "Do not include directly."
	14	#endif
	15
198016e1 SH	16	#define MXC_CPU_MX1 1
198016e1 SH	17	#define MXC_CPU_MX21 21
8c25c36f	18	#define MXC_CPU_MX25 25
198016e1 SH	19	#define MXC_CPU_MX27 27
	20	#define MXC_CPU_MX31 31
	21	#define MXC_CPU_MX35 35
438caa3f	22	#define MXC_CPU_MX51 51
c0abefd3	23	#define MXC_CPU_MX53 53
a2887546	24	#define MXC_CPU_IMX6SL 0x60
3c03a2fe	25	#define MXC_CPU_IMX6DL 0x61
d9654dce	26	#define MXC_CPU_IMX6SX 0x62
3c03a2fe	27	#define MXC_CPU_IMX6Q 0x63
022d0716	28	#define MXC_CPU_IMX6UL 0x64
b3ea5757	29	#define MXC_CPU_IMX6ULL 0x65
c90dec00 AH	30	/* virtual cpu id for i.mx6ulz */
c90dec00 AH	31	#define MXC_CPU_IMX6ULZ 0x6b
dee5dee2	32	#define MXC_CPU_IMX6SLL 0x67
5739b919	33	#define MXC_CPU_IMX7D 0x72
de70d0e9	34	#define MXC_CPU_IMX7ULP 0xff
198016e1	35
ec336b28 AH	36	#define IMX_DDR_TYPE_LPDDR2 1
ec336b28 AH	37
198016e1 SH	38	#ifndef __ASSEMBLY__
198016e1 SH	39	extern unsigned int __mxc_cpu_type;
5512e88f	40
a82eb09f	41	#ifdef CONFIG_SOC_IMX6SL
9ba64fe3 SG	42	static inline bool cpu_is_imx6sl(void)
	43	{
	44	return __mxc_cpu_type == MXC_CPU_IMX6SL;
	45	}
a82eb09f AB	46	#else
	47	static inline bool cpu_is_imx6sl(void)
	48	{
	49	return false;
	50	}
	51	#endif
9ba64fe3	52
3c03a2fe SG	53	static inline bool cpu_is_imx6dl(void)
	54	{
	55	return __mxc_cpu_type == MXC_CPU_IMX6DL;
	56	}
	57
d9654dce SG	58	static inline bool cpu_is_imx6sx(void)
	59	{
	60	return __mxc_cpu_type == MXC_CPU_IMX6SX;
	61	}
	62
022d0716 FL	63	static inline bool cpu_is_imx6ul(void)
	64	{
	65	return __mxc_cpu_type == MXC_CPU_IMX6UL;
	66	}
	67
b3ea5757 LC	68	static inline bool cpu_is_imx6ull(void)
	69	{
	70	return __mxc_cpu_type == MXC_CPU_IMX6ULL;
	71	}
	72
c90dec00 AH	73	static inline bool cpu_is_imx6ulz(void)
	74	{
	75	return __mxc_cpu_type == MXC_CPU_IMX6ULZ;
	76	}
	77
dee5dee2 BP	78	static inline bool cpu_is_imx6sll(void)
	79	{
	80	return __mxc_cpu_type == MXC_CPU_IMX6SLL;
	81	}
	82
3c03a2fe SG	83	static inline bool cpu_is_imx6q(void)
	84	{
	85	return __mxc_cpu_type == MXC_CPU_IMX6Q;
	86	}
64f102b6	87
5739b919 AH	88	static inline bool cpu_is_imx7d(void)
	89	{
	90	return __mxc_cpu_type == MXC_CPU_IMX7D;
	91	}
	92
64f102b6 YS	93	struct cpu_op {
	94	u32 cpu_rate;
	95	};
	96
010dc8af	97	int tzic_enable_wake(void);
0adf882b	98
64f102b6 YS	99	extern struct cpu_op (get_cpu_op)(int *op);
	100	#endif
	101
c553138f JB	102	#define imx_readl readl_relaxed
	103	#define imx_readw readw_relaxed
	104	#define imx_writel writel_relaxed
	105	#define imx_writew writew_relaxed
	106
f304fc42	107	#endif /* __ASM_ARCH_MXC_H__ */