projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 16216333 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 260a1fd2 HS |
2 | /* |
| 3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
| 4 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
| 5 | * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de | |
| 6 | * | |
| 7 | * This contains i.MX21-specific hardware definitions. For those | |
| 8 | * hardware pieces that are common between i.MX21 and i.MX27, have a | |
| 9 | * look at mx2x.h. | |
| 260a1fd2 HS |
10 | */ |
| 11 | ||
| 3cdd5441 UKK |
12 | #ifndef __MACH_MX21_H__ |
| 13 | #define __MACH_MX21_H__ | |
| 260a1fd2 | 14 | |
| 4c12b3c2 | 15 | #define MX21_AIPI_BASE_ADDR 0x10000000 |
| 4c12b3c2 UKK |
16 | #define MX21_AIPI_SIZE SZ_1M |
| 17 | #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) | |
| 18 | #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) | |
| 19 | #define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000) | |
| 20 | #define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000) | |
| 21 | #define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000) | |
| 22 | #define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000) | |
| 23 | #define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000) | |
| 24 | #define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000) | |
| 25 | #define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000) | |
| 26 | #define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000) | |
| 27 | #define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000) | |
| 28 | #define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000) | |
| 29 | #define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000) | |
| 30 | #define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000) | |
| 31 | #define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000) | |
| 32 | #define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000) | |
| 33 | #define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000) | |
| 34 | #define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000) | |
| 35 | #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) | |
| 36 | #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) | |
| 37 | #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) | |
| d485c7e7 UKK |
38 | #define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) |
| 39 | #define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) | |
| 40 | #define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) | |
| 41 | #define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) | |
| 42 | #define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) | |
| 43 | #define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) | |
| 4c12b3c2 UKK |
44 | #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) |
| 45 | #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) | |
| 46 | #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) | |
| 47 | #define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000) | |
| 48 | #define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000) | |
| 49 | #define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000) | |
| 50 | #define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400) | |
| 51 | #define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000) | |
| 52 | #define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800) | |
| 53 | #define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000) | |
| 54 | #define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000) | |
| 55 | ||
| 56 | #define MX21_AVIC_BASE_ADDR 0x10040000 | |
| 57 | ||
| 58 | #define MX21_SAHB1_BASE_ADDR 0x80000000 | |
| 4c12b3c2 UKK |
59 | #define MX21_SAHB1_SIZE SZ_1M |
| 60 | #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) | |
| 61 | ||
| 260a1fd2 | 62 | /* Memory regions and CS */ |
| c1129313 UKK |
63 | #define MX21_SDRAM_BASE_ADDR 0xc0000000 |
| 64 | #define MX21_CSD1_BASE_ADDR 0xc4000000 | |
| 260a1fd2 | 65 | |
| c1129313 UKK |
66 | #define MX21_CS0_BASE_ADDR 0xc8000000 |
| 67 | #define MX21_CS1_BASE_ADDR 0xcc000000 | |
| 68 | #define MX21_CS2_BASE_ADDR 0xd0000000 | |
| 69 | #define MX21_CS3_BASE_ADDR 0xd1000000 | |
| 70 | #define MX21_CS4_BASE_ADDR 0xd2000000 | |
| 71 | #define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000 | |
| 72 | #define MX21_CS5_BASE_ADDR 0xdd000000 | |
| 260a1fd2 HS |
73 | |
| 74 | /* NAND, SDRAM, WEIM etc controllers */ | |
| c1129313 | 75 | #define MX21_X_MEMC_BASE_ADDR 0xdf000000 |
| c1129313 | 76 | #define MX21_X_MEMC_SIZE SZ_256K |
| 260a1fd2 | 77 | |
| c1129313 UKK |
78 | #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) |
| 79 | #define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000) | |
| 80 | #define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000) | |
| 81 | #define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000) | |
| 260a1fd2 | 82 | |
| c1129313 | 83 | #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ |
| 260a1fd2 | 84 | |
| a9963148 | 85 | #define MX21_IO_P2V(x) IMX_IO_P2V(x) |
| f5d7a13b | 86 | #define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) |
| a3f5ac78 | 87 | |
| 260a1fd2 | 88 | /* fixed interrupt numbers */ |
| 8842a9e2 SG |
89 | #include <asm/irq.h> |
| 90 | #define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6) | |
| 91 | #define MX21_INT_GPIO (NR_IRQS_LEGACY + 8) | |
| 92 | #define MX21_INT_FIRI (NR_IRQS_LEGACY + 9) | |
| 93 | #define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10) | |
| 94 | #define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11) | |
| 95 | #define MX21_INT_I2C (NR_IRQS_LEGACY + 12) | |
| 96 | #define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13) | |
| 97 | #define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14) | |
| 98 | #define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15) | |
| 99 | #define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16) | |
| 100 | #define MX21_INT_UART4 (NR_IRQS_LEGACY + 17) | |
| 101 | #define MX21_INT_UART3 (NR_IRQS_LEGACY + 18) | |
| 102 | #define MX21_INT_UART2 (NR_IRQS_LEGACY + 19) | |
| 103 | #define MX21_INT_UART1 (NR_IRQS_LEGACY + 20) | |
| 104 | #define MX21_INT_KPP (NR_IRQS_LEGACY + 21) | |
| 105 | #define MX21_INT_RTC (NR_IRQS_LEGACY + 22) | |
| 106 | #define MX21_INT_PWM (NR_IRQS_LEGACY + 23) | |
| 107 | #define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24) | |
| 108 | #define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25) | |
| 109 | #define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26) | |
| 110 | #define MX21_INT_WDOG (NR_IRQS_LEGACY + 27) | |
| 111 | #define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28) | |
| 112 | #define MX21_INT_NFC (NR_IRQS_LEGACY + 29) | |
| 113 | #define MX21_INT_BMI (NR_IRQS_LEGACY + 30) | |
| 114 | #define MX21_INT_CSI (NR_IRQS_LEGACY + 31) | |
| 115 | #define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32) | |
| 116 | #define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33) | |
| 117 | #define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34) | |
| 118 | #define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35) | |
| 119 | #define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36) | |
| 120 | #define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37) | |
| 121 | #define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38) | |
| 122 | #define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39) | |
| 123 | #define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40) | |
| 124 | #define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41) | |
| 125 | #define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42) | |
| 126 | #define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43) | |
| 127 | #define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44) | |
| 128 | #define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45) | |
| 129 | #define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46) | |
| 130 | #define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47) | |
| 131 | #define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49) | |
| 132 | #define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50) | |
| 133 | #define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51) | |
| 134 | #define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52) | |
| 135 | #define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53) | |
| 136 | #define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54) | |
| 137 | #define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55) | |
| 138 | #define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56) | |
| 139 | #define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57) | |
| 140 | #define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58) | |
| 141 | #define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60) | |
| 142 | #define MX21_INT_LCDC (NR_IRQS_LEGACY + 61) | |
| 260a1fd2 HS |
143 | |
| 144 | /* fixed DMA request numbers */ | |
| 4c12b3c2 UKK |
145 | #define MX21_DMA_REQ_CSPI3_RX 1 |
| 146 | #define MX21_DMA_REQ_CSPI3_TX 2 | |
| 147 | #define MX21_DMA_REQ_EXT 3 | |
| c1129313 | 148 | #define MX21_DMA_REQ_FIRI_RX 4 |
| 4c12b3c2 UKK |
149 | #define MX21_DMA_REQ_SDHC2 6 |
| 150 | #define MX21_DMA_REQ_SDHC1 7 | |
| 151 | #define MX21_DMA_REQ_SSI2_RX0 8 | |
| 152 | #define MX21_DMA_REQ_SSI2_TX0 9 | |
| 153 | #define MX21_DMA_REQ_SSI2_RX1 10 | |
| 154 | #define MX21_DMA_REQ_SSI2_TX1 11 | |
| 155 | #define MX21_DMA_REQ_SSI1_RX0 12 | |
| 156 | #define MX21_DMA_REQ_SSI1_TX0 13 | |
| 157 | #define MX21_DMA_REQ_SSI1_RX1 14 | |
| 158 | #define MX21_DMA_REQ_SSI1_TX1 15 | |
| 159 | #define MX21_DMA_REQ_CSPI2_RX 16 | |
| 160 | #define MX21_DMA_REQ_CSPI2_TX 17 | |
| 161 | #define MX21_DMA_REQ_CSPI1_RX 18 | |
| 162 | #define MX21_DMA_REQ_CSPI1_TX 19 | |
| 163 | #define MX21_DMA_REQ_UART4_RX 20 | |
| 164 | #define MX21_DMA_REQ_UART4_TX 21 | |
| 165 | #define MX21_DMA_REQ_UART3_RX 22 | |
| 166 | #define MX21_DMA_REQ_UART3_TX 23 | |
| 167 | #define MX21_DMA_REQ_UART2_RX 24 | |
| 168 | #define MX21_DMA_REQ_UART2_TX 25 | |
| 169 | #define MX21_DMA_REQ_UART1_RX 26 | |
| 170 | #define MX21_DMA_REQ_UART1_TX 27 | |
| c1129313 UKK |
171 | #define MX21_DMA_REQ_BMI_TX 28 |
| 172 | #define MX21_DMA_REQ_BMI_RX 29 | |
| 4c12b3c2 UKK |
173 | #define MX21_DMA_REQ_CSI_STAT 30 |
| 174 | #define MX21_DMA_REQ_CSI_RX 31 | |
| c1129313 | 175 | |
| 3cdd5441 | 176 | #endif /* ifndef __MACH_MX21_H__ */ |