Commit | Line | Data |
---|---|---|
aefa1c6e FE |
1 | /* |
2 | * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
d17e1c1a | 3 | * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix |
aefa1c6e FE |
4 | * |
5 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | |
6 | * | |
25af2d9f AG |
7 | * Copyright (C) 2011 Meprolight, Ltd. |
8 | * Alex Gershgorin <alexg@meprolight.com> | |
9 | * | |
10 | * Modified from i.MX31 3-Stack Development System | |
11 | * | |
aefa1c6e FE |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
aefa1c6e FE |
21 | */ |
22 | ||
767c38b2 UKK |
23 | /* |
24 | * This machine is known as: | |
25 | * - i.MX35 3-Stack Development System | |
26 | * - i.MX35 Platform Development Kit (i.MX35 PDK) | |
27 | */ | |
28 | ||
aefa1c6e FE |
29 | #include <linux/types.h> |
30 | #include <linux/init.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/memory.h> | |
33 | #include <linux/gpio.h> | |
130a0dda | 34 | #include <linux/usb/otg.h> |
aefa1c6e | 35 | |
d17e1c1a | 36 | #include <linux/mtd/physmap.h> |
c8349fb4 AG |
37 | #include <linux/mfd/mc13892.h> |
38 | #include <linux/regulator/machine.h> | |
d17e1c1a | 39 | |
aefa1c6e FE |
40 | #include <asm/mach-types.h> |
41 | #include <asm/mach/arch.h> | |
42 | #include <asm/mach/time.h> | |
43 | #include <asm/mach/map.h> | |
25af2d9f | 44 | #include <asm/memblock.h> |
aefa1c6e FE |
45 | |
46 | #include <mach/hardware.h> | |
47 | #include <mach/common.h> | |
aefa1c6e | 48 | #include <mach/iomux-mx35.h> |
2c6605de XJ |
49 | #include <mach/irqs.h> |
50 | #include <mach/3ds_debugboard.h> | |
881e09f8 | 51 | #include <video/platform_lcd.h> |
aefa1c6e | 52 | |
25af2d9f AG |
53 | #include <media/soc_camera.h> |
54 | ||
6eafde5f | 55 | #include "devices-imx35.h" |
aefa1c6e | 56 | |
881e09f8 | 57 | #define GPIO_MC9S08DZ60_GPS_ENABLE 0 |
58 | #define GPIO_MC9S08DZ60_HDD_ENABLE 4 | |
59 | #define GPIO_MC9S08DZ60_WIFI_ENABLE 5 | |
60 | #define GPIO_MC9S08DZ60_LCD_ENABLE 6 | |
61 | #define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8 | |
62 | ||
63 | static const struct fb_videomode fb_modedb[] = { | |
64 | { | |
65 | /* 800x480 @ 55 Hz */ | |
66 | .name = "Ceramate-CLAA070VC01", | |
67 | .refresh = 55, | |
68 | .xres = 800, | |
69 | .yres = 480, | |
70 | .pixclock = 40000, | |
71 | .left_margin = 40, | |
72 | .right_margin = 40, | |
73 | .upper_margin = 5, | |
74 | .lower_margin = 5, | |
75 | .hsync_len = 20, | |
76 | .vsync_len = 10, | |
77 | .sync = FB_SYNC_OE_ACT_HIGH, | |
78 | .vmode = FB_VMODE_NONINTERLACED, | |
79 | .flag = 0, | |
80 | }, | |
81 | }; | |
82 | ||
83 | static const struct ipu_platform_data mx3_ipu_data __initconst = { | |
84 | .irq_base = MXC_IPU_IRQ_START, | |
85 | }; | |
86 | ||
87 | static struct mx3fb_platform_data mx3fb_pdata __initdata = { | |
88 | .name = "Ceramate-CLAA070VC01", | |
89 | .mode = fb_modedb, | |
90 | .num_modes = ARRAY_SIZE(fb_modedb), | |
91 | }; | |
92 | ||
93 | static struct i2c_board_info __initdata i2c_devices_3ds[] = { | |
94 | { | |
95 | I2C_BOARD_INFO("mc9s08dz60", 0x69), | |
96 | }, | |
97 | }; | |
98 | ||
99 | static int lcd_power_gpio = -ENXIO; | |
100 | ||
101 | static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip, | |
eb26e877 | 102 | const void *data) |
881e09f8 | 103 | { |
104 | return !strcmp(chip->label, data); | |
105 | } | |
106 | ||
107 | static void mx35_3ds_lcd_set_power( | |
108 | struct plat_lcd_data *pd, unsigned int power) | |
109 | { | |
110 | struct gpio_chip *chip; | |
111 | ||
112 | if (!gpio_is_valid(lcd_power_gpio)) { | |
113 | chip = gpiochip_find( | |
114 | "mc9s08dz60", mc9s08dz60_gpiochip_match); | |
115 | if (chip) { | |
116 | lcd_power_gpio = | |
117 | chip->base + GPIO_MC9S08DZ60_LCD_ENABLE; | |
118 | if (gpio_request(lcd_power_gpio, "lcd_power") < 0) { | |
119 | pr_err("error: gpio already requested!\n"); | |
120 | lcd_power_gpio = -ENXIO; | |
121 | } | |
122 | } else { | |
123 | pr_err("error: didn't find mc9s08dz60 gpio chip\n"); | |
124 | } | |
125 | } | |
126 | ||
127 | if (gpio_is_valid(lcd_power_gpio)) | |
128 | gpio_set_value_cansleep(lcd_power_gpio, power); | |
129 | } | |
130 | ||
131 | static struct plat_lcd_data mx35_3ds_lcd_data = { | |
132 | .set_power = mx35_3ds_lcd_set_power, | |
133 | }; | |
134 | ||
135 | static struct platform_device mx35_3ds_lcd = { | |
136 | .name = "platform-lcd", | |
137 | .dev.platform_data = &mx35_3ds_lcd_data, | |
138 | }; | |
139 | ||
7cf7381f | 140 | #define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 1)) |
2c6605de | 141 | |
6eafde5f | 142 | static const struct imxuart_platform_data uart_pdata __initconst = { |
aefa1c6e FE |
143 | .flags = IMXUART_HAVE_RTSCTS, |
144 | }; | |
145 | ||
d17e1c1a MKB |
146 | static struct physmap_flash_data mx35pdk_flash_data = { |
147 | .width = 2, | |
148 | }; | |
149 | ||
150 | static struct resource mx35pdk_flash_resource = { | |
151 | .start = MX35_CS0_BASE_ADDR, | |
152 | .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, | |
153 | .flags = IORESOURCE_MEM, | |
154 | }; | |
155 | ||
156 | static struct platform_device mx35pdk_flash = { | |
157 | .name = "physmap-flash", | |
158 | .id = 0, | |
159 | .dev = { | |
160 | .platform_data = &mx35pdk_flash_data, | |
161 | }, | |
162 | .resource = &mx35pdk_flash_resource, | |
163 | .num_resources = 1, | |
164 | }; | |
165 | ||
81aa1720 MKB |
166 | static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = { |
167 | .width = 1, | |
168 | .hw_ecc = 1, | |
169 | .flash_bbt = 1, | |
170 | }; | |
171 | ||
aefa1c6e | 172 | static struct platform_device *devices[] __initdata = { |
d17e1c1a | 173 | &mx35pdk_flash, |
aefa1c6e FE |
174 | }; |
175 | ||
8f5260c8 | 176 | static iomux_v3_cfg_t mx35pdk_pads[] = { |
aefa1c6e FE |
177 | /* UART1 */ |
178 | MX35_PAD_CTS1__UART1_CTS, | |
179 | MX35_PAD_RTS1__UART1_RTS, | |
180 | MX35_PAD_TXD1__UART1_TXD_MUX, | |
181 | MX35_PAD_RXD1__UART1_RXD_MUX, | |
182 | /* FEC */ | |
183 | MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, | |
184 | MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, | |
185 | MX35_PAD_FEC_RX_DV__FEC_RX_DV, | |
186 | MX35_PAD_FEC_COL__FEC_COL, | |
187 | MX35_PAD_FEC_RDATA0__FEC_RDATA_0, | |
188 | MX35_PAD_FEC_TDATA0__FEC_TDATA_0, | |
189 | MX35_PAD_FEC_TX_EN__FEC_TX_EN, | |
190 | MX35_PAD_FEC_MDC__FEC_MDC, | |
191 | MX35_PAD_FEC_MDIO__FEC_MDIO, | |
192 | MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, | |
193 | MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, | |
194 | MX35_PAD_FEC_CRS__FEC_CRS, | |
195 | MX35_PAD_FEC_RDATA1__FEC_RDATA_1, | |
196 | MX35_PAD_FEC_TDATA1__FEC_TDATA_1, | |
197 | MX35_PAD_FEC_RDATA2__FEC_RDATA_2, | |
198 | MX35_PAD_FEC_TDATA2__FEC_TDATA_2, | |
199 | MX35_PAD_FEC_RDATA3__FEC_RDATA_3, | |
200 | MX35_PAD_FEC_TDATA3__FEC_TDATA_3, | |
9c2daf15 HH |
201 | /* USBOTG */ |
202 | MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, | |
203 | MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, | |
ab3d8b58 MKB |
204 | /* USBH1 */ |
205 | MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, | |
206 | MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, | |
6207c833 SG |
207 | /* SDCARD */ |
208 | MX35_PAD_SD1_CMD__ESDHC1_CMD, | |
209 | MX35_PAD_SD1_CLK__ESDHC1_CLK, | |
210 | MX35_PAD_SD1_DATA0__ESDHC1_DAT0, | |
211 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1, | |
212 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2, | |
213 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3, | |
352cd9a0 FE |
214 | /* I2C1 */ |
215 | MX35_PAD_I2C1_CLK__I2C1_SCL, | |
216 | MX35_PAD_I2C1_DAT__I2C1_SDA, | |
881e09f8 | 217 | /* Display */ |
218 | MX35_PAD_LD0__IPU_DISPB_DAT_0, | |
219 | MX35_PAD_LD1__IPU_DISPB_DAT_1, | |
220 | MX35_PAD_LD2__IPU_DISPB_DAT_2, | |
221 | MX35_PAD_LD3__IPU_DISPB_DAT_3, | |
222 | MX35_PAD_LD4__IPU_DISPB_DAT_4, | |
223 | MX35_PAD_LD5__IPU_DISPB_DAT_5, | |
224 | MX35_PAD_LD6__IPU_DISPB_DAT_6, | |
225 | MX35_PAD_LD7__IPU_DISPB_DAT_7, | |
226 | MX35_PAD_LD8__IPU_DISPB_DAT_8, | |
227 | MX35_PAD_LD9__IPU_DISPB_DAT_9, | |
228 | MX35_PAD_LD10__IPU_DISPB_DAT_10, | |
229 | MX35_PAD_LD11__IPU_DISPB_DAT_11, | |
230 | MX35_PAD_LD12__IPU_DISPB_DAT_12, | |
231 | MX35_PAD_LD13__IPU_DISPB_DAT_13, | |
232 | MX35_PAD_LD14__IPU_DISPB_DAT_14, | |
233 | MX35_PAD_LD15__IPU_DISPB_DAT_15, | |
234 | MX35_PAD_LD16__IPU_DISPB_DAT_16, | |
235 | MX35_PAD_LD17__IPU_DISPB_DAT_17, | |
236 | MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, | |
237 | MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, | |
238 | MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, | |
239 | MX35_PAD_CONTRAST__IPU_DISPB_CONTR, | |
240 | MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, | |
241 | MX35_PAD_D3_REV__IPU_DISPB_D3_REV, | |
242 | MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, | |
25af2d9f AG |
243 | /* CSI */ |
244 | MX35_PAD_TX1__IPU_CSI_D_6, | |
245 | MX35_PAD_TX0__IPU_CSI_D_7, | |
246 | MX35_PAD_CSI_D8__IPU_CSI_D_8, | |
247 | MX35_PAD_CSI_D9__IPU_CSI_D_9, | |
248 | MX35_PAD_CSI_D10__IPU_CSI_D_10, | |
249 | MX35_PAD_CSI_D11__IPU_CSI_D_11, | |
250 | MX35_PAD_CSI_D12__IPU_CSI_D_12, | |
251 | MX35_PAD_CSI_D13__IPU_CSI_D_13, | |
252 | MX35_PAD_CSI_D14__IPU_CSI_D_14, | |
253 | MX35_PAD_CSI_D15__IPU_CSI_D_15, | |
254 | MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC, | |
255 | MX35_PAD_CSI_MCLK__IPU_CSI_MCLK, | |
256 | MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK, | |
257 | MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC, | |
c8349fb4 AG |
258 | /*PMIC IRQ*/ |
259 | MX35_PAD_GPIO2_0__GPIO2_0, | |
25af2d9f AG |
260 | }; |
261 | ||
262 | /* | |
263 | * Camera support | |
264 | */ | |
265 | static phys_addr_t mx3_camera_base __initdata; | |
266 | #define MX35_3DS_CAMERA_BUF_SIZE SZ_8M | |
267 | ||
268 | static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = { | |
269 | .flags = MX3_CAMERA_DATAWIDTH_8, | |
270 | .mclk_10khz = 2000, | |
271 | }; | |
272 | ||
273 | static int __init imx35_3ds_init_camera(void) | |
274 | { | |
275 | int dma, ret = -ENOMEM; | |
276 | struct platform_device *pdev = | |
277 | imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata); | |
278 | ||
279 | if (IS_ERR(pdev)) | |
280 | return PTR_ERR(pdev); | |
281 | ||
282 | if (!mx3_camera_base) | |
283 | goto err; | |
284 | ||
285 | dma = dma_declare_coherent_memory(&pdev->dev, | |
286 | mx3_camera_base, mx3_camera_base, | |
287 | MX35_3DS_CAMERA_BUF_SIZE, | |
288 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); | |
289 | ||
290 | if (!(dma & DMA_MEMORY_MAP)) | |
291 | goto err; | |
292 | ||
293 | ret = platform_device_add(pdev); | |
294 | if (ret) | |
295 | err: | |
296 | platform_device_put(pdev); | |
297 | ||
298 | return ret; | |
299 | } | |
300 | ||
301 | static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = { | |
302 | .irq_base = MXC_IPU_IRQ_START, | |
303 | }; | |
304 | ||
305 | static struct i2c_board_info mx35_3ds_i2c_camera = { | |
306 | I2C_BOARD_INFO("ov2640", 0x30), | |
307 | }; | |
308 | ||
309 | static struct soc_camera_link iclink_ov2640 = { | |
310 | .bus_id = 0, | |
311 | .board_info = &mx35_3ds_i2c_camera, | |
312 | .i2c_adapter_id = 0, | |
313 | .power = NULL, | |
314 | }; | |
315 | ||
316 | static struct platform_device mx35_3ds_ov2640 = { | |
317 | .name = "soc-camera-pdrv", | |
318 | .id = 0, | |
319 | .dev = { | |
320 | .platform_data = &iclink_ov2640, | |
321 | }, | |
9c2daf15 HH |
322 | }; |
323 | ||
c8349fb4 AG |
324 | static struct regulator_consumer_supply sw1_consumers[] = { |
325 | { | |
326 | .supply = "cpu_vcc", | |
327 | } | |
328 | }; | |
329 | ||
330 | static struct regulator_consumer_supply vcam_consumers[] = { | |
331 | /* sgtl5000 */ | |
332 | REGULATOR_SUPPLY("VDDA", "0-000a"), | |
333 | }; | |
334 | ||
335 | static struct regulator_consumer_supply vaudio_consumers[] = { | |
336 | REGULATOR_SUPPLY("cmos_vio", "soc-camera-pdrv.0"), | |
337 | }; | |
338 | ||
339 | static struct regulator_init_data sw1_init = { | |
340 | .constraints = { | |
341 | .name = "SW1", | |
342 | .min_uV = 600000, | |
343 | .max_uV = 1375000, | |
344 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | |
345 | .valid_modes_mask = 0, | |
346 | .always_on = 1, | |
347 | .boot_on = 1, | |
348 | }, | |
349 | .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), | |
350 | .consumer_supplies = sw1_consumers, | |
351 | }; | |
352 | ||
353 | static struct regulator_init_data sw2_init = { | |
354 | .constraints = { | |
355 | .name = "SW2", | |
356 | .always_on = 1, | |
357 | .boot_on = 1, | |
358 | } | |
359 | }; | |
360 | ||
361 | static struct regulator_init_data sw3_init = { | |
362 | .constraints = { | |
363 | .name = "SW3", | |
364 | .always_on = 1, | |
365 | .boot_on = 1, | |
366 | } | |
367 | }; | |
368 | ||
369 | static struct regulator_init_data sw4_init = { | |
370 | .constraints = { | |
371 | .name = "SW4", | |
372 | .always_on = 1, | |
373 | .boot_on = 1, | |
374 | } | |
375 | }; | |
376 | ||
377 | static struct regulator_init_data viohi_init = { | |
378 | .constraints = { | |
379 | .name = "VIOHI", | |
380 | .boot_on = 1, | |
381 | } | |
382 | }; | |
383 | ||
384 | static struct regulator_init_data vusb_init = { | |
385 | .constraints = { | |
386 | .name = "VUSB", | |
387 | .boot_on = 1, | |
388 | } | |
389 | }; | |
390 | ||
391 | static struct regulator_init_data vdig_init = { | |
392 | .constraints = { | |
393 | .name = "VDIG", | |
394 | .boot_on = 1, | |
395 | } | |
396 | }; | |
397 | ||
398 | static struct regulator_init_data vpll_init = { | |
399 | .constraints = { | |
400 | .name = "VPLL", | |
401 | .boot_on = 1, | |
402 | } | |
403 | }; | |
404 | ||
405 | static struct regulator_init_data vusb2_init = { | |
406 | .constraints = { | |
407 | .name = "VUSB2", | |
408 | .boot_on = 1, | |
409 | } | |
410 | }; | |
411 | ||
412 | static struct regulator_init_data vvideo_init = { | |
413 | .constraints = { | |
414 | .name = "VVIDEO", | |
415 | .boot_on = 1 | |
416 | } | |
417 | }; | |
418 | ||
419 | static struct regulator_init_data vaudio_init = { | |
420 | .constraints = { | |
421 | .name = "VAUDIO", | |
422 | .min_uV = 2300000, | |
423 | .max_uV = 3000000, | |
424 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | |
425 | .boot_on = 1 | |
426 | }, | |
427 | .num_consumer_supplies = ARRAY_SIZE(vaudio_consumers), | |
428 | .consumer_supplies = vaudio_consumers, | |
429 | }; | |
430 | ||
431 | static struct regulator_init_data vcam_init = { | |
432 | .constraints = { | |
433 | .name = "VCAM", | |
434 | .min_uV = 2500000, | |
435 | .max_uV = 3000000, | |
436 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
437 | REGULATOR_CHANGE_MODE, | |
438 | .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, | |
439 | .boot_on = 1 | |
440 | }, | |
441 | .num_consumer_supplies = ARRAY_SIZE(vcam_consumers), | |
442 | .consumer_supplies = vcam_consumers, | |
443 | }; | |
444 | ||
445 | static struct regulator_init_data vgen1_init = { | |
446 | .constraints = { | |
447 | .name = "VGEN1", | |
448 | } | |
449 | }; | |
450 | ||
451 | static struct regulator_init_data vgen2_init = { | |
452 | .constraints = { | |
453 | .name = "VGEN2", | |
454 | .boot_on = 1, | |
455 | } | |
456 | }; | |
457 | ||
458 | static struct regulator_init_data vgen3_init = { | |
459 | .constraints = { | |
460 | .name = "VGEN3", | |
461 | } | |
462 | }; | |
463 | ||
464 | static struct mc13xxx_regulator_init_data mx35_3ds_regulators[] = { | |
465 | { .id = MC13892_SW1, .init_data = &sw1_init }, | |
466 | { .id = MC13892_SW2, .init_data = &sw2_init }, | |
467 | { .id = MC13892_SW3, .init_data = &sw3_init }, | |
468 | { .id = MC13892_SW4, .init_data = &sw4_init }, | |
469 | { .id = MC13892_VIOHI, .init_data = &viohi_init }, | |
470 | { .id = MC13892_VPLL, .init_data = &vpll_init }, | |
471 | { .id = MC13892_VDIG, .init_data = &vdig_init }, | |
472 | { .id = MC13892_VUSB2, .init_data = &vusb2_init }, | |
473 | { .id = MC13892_VVIDEO, .init_data = &vvideo_init }, | |
474 | { .id = MC13892_VAUDIO, .init_data = &vaudio_init }, | |
475 | { .id = MC13892_VCAM, .init_data = &vcam_init }, | |
476 | { .id = MC13892_VGEN1, .init_data = &vgen1_init }, | |
477 | { .id = MC13892_VGEN2, .init_data = &vgen2_init }, | |
478 | { .id = MC13892_VGEN3, .init_data = &vgen3_init }, | |
479 | { .id = MC13892_VUSB, .init_data = &vusb_init }, | |
480 | }; | |
481 | ||
482 | static struct mc13xxx_platform_data mx35_3ds_mc13892_data = { | |
483 | .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN, | |
484 | .regulators = { | |
485 | .num_regulators = ARRAY_SIZE(mx35_3ds_regulators), | |
486 | .regulators = mx35_3ds_regulators, | |
487 | }, | |
488 | }; | |
489 | ||
490 | #define GPIO_PMIC_INT IMX_GPIO_NR(2, 0) | |
491 | ||
492 | static struct i2c_board_info mx35_3ds_i2c_mc13892 = { | |
493 | ||
494 | I2C_BOARD_INFO("mc13892", 0x08), | |
495 | .platform_data = &mx35_3ds_mc13892_data, | |
496 | .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT), | |
497 | }; | |
498 | ||
499 | static void __init imx35_3ds_init_mc13892(void) | |
500 | { | |
501 | int ret = gpio_request_one(GPIO_PMIC_INT, GPIOF_DIR_IN, "pmic irq"); | |
502 | ||
503 | if (ret) { | |
504 | pr_err("failed to get pmic irq: %d\n", ret); | |
505 | return; | |
506 | } | |
507 | ||
508 | i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1); | |
509 | } | |
510 | ||
4bd597b6 SH |
511 | static int mx35_3ds_otg_init(struct platform_device *pdev) |
512 | { | |
513 | return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); | |
514 | } | |
515 | ||
9c2daf15 | 516 | /* OTG config */ |
9e1dde33 | 517 | static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { |
9c2daf15 HH |
518 | .operating_mode = FSL_USB2_DR_DEVICE, |
519 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, | |
1a46cce8 FE |
520 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, |
521 | /* | |
522 | * ENGCM09152 also requires a hardware change. | |
523 | * Please check the MX35 Chip Errata document for details. | |
524 | */ | |
aefa1c6e FE |
525 | }; |
526 | ||
130a0dda | 527 | static struct mxc_usbh_platform_data otg_pdata __initdata = { |
4bd597b6 | 528 | .init = mx35_3ds_otg_init, |
130a0dda | 529 | .portsc = MXC_EHCI_MODE_UTMI, |
130a0dda FE |
530 | }; |
531 | ||
4bd597b6 SH |
532 | static int mx35_3ds_usbh_init(struct platform_device *pdev) |
533 | { | |
534 | return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | | |
535 | MXC_EHCI_INTERNAL_PHY); | |
536 | } | |
537 | ||
ab3d8b58 | 538 | /* USB HOST config */ |
2d58de28 | 539 | static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { |
4bd597b6 | 540 | .init = mx35_3ds_usbh_init, |
ab3d8b58 | 541 | .portsc = MXC_EHCI_MODE_SERIAL, |
ab3d8b58 MKB |
542 | }; |
543 | ||
130a0dda FE |
544 | static int otg_mode_host; |
545 | ||
546 | static int __init mx35_3ds_otg_mode(char *options) | |
547 | { | |
548 | if (!strcmp(options, "host")) | |
549 | otg_mode_host = 1; | |
550 | else if (!strcmp(options, "device")) | |
551 | otg_mode_host = 0; | |
552 | else | |
553 | pr_info("otg_mode neither \"host\" nor \"device\". " | |
554 | "Defaulting to device\n"); | |
555 | return 0; | |
556 | } | |
557 | __setup("otg_mode=", mx35_3ds_otg_mode); | |
558 | ||
352cd9a0 FE |
559 | static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = { |
560 | .bitrate = 100000, | |
561 | }; | |
562 | ||
aefa1c6e FE |
563 | /* |
564 | * Board specific initialization. | |
565 | */ | |
e134fb2b | 566 | static void __init mx35_3ds_init(void) |
aefa1c6e | 567 | { |
881e09f8 | 568 | struct platform_device *imx35_fb_pdev; |
569 | ||
b78d8e59 SG |
570 | imx35_soc_init(); |
571 | ||
aefa1c6e FE |
572 | mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); |
573 | ||
6bd96f3c | 574 | imx35_add_fec(NULL); |
c496fa6b | 575 | imx35_add_imx2_wdt(NULL); |
aefa1c6e FE |
576 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
577 | ||
6eafde5f | 578 | imx35_add_imx_uart0(&uart_pdata); |
9c2daf15 | 579 | |
130a0dda FE |
580 | if (otg_mode_host) |
581 | imx35_add_mxc_ehci_otg(&otg_pdata); | |
81aa1720 | 582 | |
2d58de28 | 583 | imx35_add_mxc_ehci_hs(&usb_host_pdata); |
ab3d8b58 | 584 | |
130a0dda FE |
585 | if (!otg_mode_host) |
586 | imx35_add_fsl_usb2_udc(&usb_otg_pdata); | |
587 | ||
81aa1720 | 588 | imx35_add_mxc_nand(&mx35pdk_nand_board_info); |
124bf94a | 589 | imx35_add_sdhci_esdhc_imx(0, NULL); |
2c6605de XJ |
590 | |
591 | if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT)) | |
592 | pr_warn("Init of the debugboard failed, all " | |
593 | "devices on the debugboard are unusable.\n"); | |
352cd9a0 | 594 | imx35_add_imx_i2c0(&mx35_3ds_i2c0_data); |
881e09f8 | 595 | |
596 | i2c_register_board_info( | |
597 | 0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds)); | |
598 | ||
25af2d9f AG |
599 | imx35_add_ipu_core(&mx35_3ds_ipu_data); |
600 | platform_device_register(&mx35_3ds_ov2640); | |
601 | imx35_3ds_init_camera(); | |
602 | ||
881e09f8 | 603 | imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata); |
604 | mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev; | |
605 | platform_device_register(&mx35_3ds_lcd); | |
c8349fb4 AG |
606 | |
607 | imx35_3ds_init_mc13892(); | |
aefa1c6e FE |
608 | } |
609 | ||
610 | static void __init mx35pdk_timer_init(void) | |
611 | { | |
612 | mx35_clocks_init(); | |
613 | } | |
614 | ||
615 | struct sys_timer mx35pdk_timer = { | |
616 | .init = mx35pdk_timer_init, | |
617 | }; | |
618 | ||
25af2d9f AG |
619 | static void __init mx35_3ds_reserve(void) |
620 | { | |
621 | /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ | |
622 | mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE, | |
623 | MX35_3DS_CAMERA_BUF_SIZE); | |
624 | } | |
625 | ||
aefa1c6e FE |
626 | MACHINE_START(MX35_3DS, "Freescale MX35PDK") |
627 | /* Maintainer: Freescale Semiconductor, Inc */ | |
dc8f1907 | 628 | .atag_offset = 0x100, |
97976e22 UKK |
629 | .map_io = mx35_map_io, |
630 | .init_early = imx35_init_early, | |
631 | .init_irq = mx35_init_irq, | |
ffa2ea3f | 632 | .handle_irq = imx35_handle_irq, |
97976e22 | 633 | .timer = &mx35pdk_timer, |
e134fb2b | 634 | .init_machine = mx35_3ds_init, |
25af2d9f | 635 | .reserve = mx35_3ds_reserve, |
65ea7884 | 636 | .restart = mxc_restart, |
aefa1c6e | 637 | MACHINE_END |