Commit | Line | Data |
---|---|---|
1553a1ec FE |
1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
1553a1ec FE |
13 | */ |
14 | ||
a2ef4562 | 15 | #include <linux/delay.h> |
b7f080cf | 16 | #include <linux/dma-mapping.h> |
1553a1ec FE |
17 | #include <linux/types.h> |
18 | #include <linux/init.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/irq.h> | |
135cad36 | 21 | #include <linux/gpio.h> |
2b0c3677 | 22 | #include <linux/platform_device.h> |
ae7a3f13 AP |
23 | #include <linux/mfd/mc13783.h> |
24 | #include <linux/spi/spi.h> | |
e42010e0 | 25 | #include <linux/spi/l4f00242t03.h> |
ae7a3f13 | 26 | #include <linux/regulator/machine.h> |
1c50e672 FE |
27 | #include <linux/usb/otg.h> |
28 | #include <linux/usb/ulpi.h> | |
164f7b52 AP |
29 | #include <linux/memblock.h> |
30 | ||
31 | #include <media/soc_camera.h> | |
1553a1ec | 32 | |
1553a1ec FE |
33 | #include <asm/mach-types.h> |
34 | #include <asm/mach/arch.h> | |
35 | #include <asm/mach/time.h> | |
36 | #include <asm/memory.h> | |
37 | #include <asm/mach/map.h> | |
716a3dc2 | 38 | #include <asm/memblock.h> |
a2ceeef5 | 39 | |
3ed0bcb4 | 40 | #include "3ds_debugboard.h" |
e3372474 | 41 | #include "common.h" |
a2ceeef5 | 42 | #include "devices-imx31.h" |
641dfe8b | 43 | #include "ehci.h" |
50f2de61 | 44 | #include "hardware.h" |
267dd34c | 45 | #include "iomux-mx3.h" |
39ef6340 | 46 | #include "ulpi.h" |
1553a1ec | 47 | |
11a332ad | 48 | static int mx31_3ds_pins[] = { |
153fa1d8 | 49 | /* UART1 */ |
63d97667 VL |
50 | MX31_PIN_CTS1__CTS1, |
51 | MX31_PIN_RTS1__RTS1, | |
52 | MX31_PIN_TXD1__TXD1, | |
135cad36 ML |
53 | MX31_PIN_RXD1__RXD1, |
54 | IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), | |
e42010e0 | 55 | /*SPI0*/ |
b2a08e3e FE |
56 | IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1), |
57 | IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1), | |
a1ac4424 AP |
58 | /* SPI 1 */ |
59 | MX31_PIN_CSPI2_SCLK__SCLK, | |
60 | MX31_PIN_CSPI2_MOSI__MOSI, | |
61 | MX31_PIN_CSPI2_MISO__MISO, | |
62 | MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, | |
63 | MX31_PIN_CSPI2_SS0__SS0, | |
64 | MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ | |
ae7a3f13 AP |
65 | /* MC13783 IRQ */ |
66 | IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), | |
a2ef4562 ML |
67 | /* USB OTG reset */ |
68 | IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO), | |
69 | /* USB OTG */ | |
70 | MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, | |
71 | MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, | |
72 | MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, | |
73 | MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, | |
74 | MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, | |
75 | MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, | |
76 | MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, | |
77 | MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, | |
78 | MX31_PIN_USBOTG_CLK__USBOTG_CLK, | |
79 | MX31_PIN_USBOTG_DIR__USBOTG_DIR, | |
80 | MX31_PIN_USBOTG_NXT__USBOTG_NXT, | |
81 | MX31_PIN_USBOTG_STP__USBOTG_STP, | |
54c1f636 AP |
82 | /*Keyboard*/ |
83 | MX31_PIN_KEY_ROW0_KEY_ROW0, | |
84 | MX31_PIN_KEY_ROW1_KEY_ROW1, | |
85 | MX31_PIN_KEY_ROW2_KEY_ROW2, | |
86 | MX31_PIN_KEY_COL0_KEY_COL0, | |
87 | MX31_PIN_KEY_COL1_KEY_COL1, | |
88 | MX31_PIN_KEY_COL2_KEY_COL2, | |
89 | MX31_PIN_KEY_COL3_KEY_COL3, | |
0d95b75e FE |
90 | /* USB Host 2 */ |
91 | IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), | |
92 | IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), | |
93 | IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), | |
94 | IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), | |
95 | IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), | |
96 | IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), | |
97 | IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1), | |
98 | IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1), | |
99 | IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1), | |
100 | IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1), | |
101 | IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1), | |
102 | IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1), | |
103 | /* USB Host2 reset */ | |
104 | IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO), | |
3d943024 FE |
105 | /* I2C1 */ |
106 | MX31_PIN_I2C_CLK__I2C1_SCL, | |
107 | MX31_PIN_I2C_DAT__I2C1_SDA, | |
0ce88b34 AP |
108 | /* SDHC1 */ |
109 | MX31_PIN_SD1_DATA3__SD1_DATA3, | |
110 | MX31_PIN_SD1_DATA2__SD1_DATA2, | |
111 | MX31_PIN_SD1_DATA1__SD1_DATA1, | |
112 | MX31_PIN_SD1_DATA0__SD1_DATA0, | |
113 | MX31_PIN_SD1_CLK__SD1_CLK, | |
114 | MX31_PIN_SD1_CMD__SD1_CMD, | |
115 | MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */ | |
116 | MX31_PIN_GPIO3_0__GPIO3_0, /* OE */ | |
e42010e0 AP |
117 | /* Framebuffer */ |
118 | MX31_PIN_LD0__LD0, | |
119 | MX31_PIN_LD1__LD1, | |
120 | MX31_PIN_LD2__LD2, | |
121 | MX31_PIN_LD3__LD3, | |
122 | MX31_PIN_LD4__LD4, | |
123 | MX31_PIN_LD5__LD5, | |
124 | MX31_PIN_LD6__LD6, | |
125 | MX31_PIN_LD7__LD7, | |
126 | MX31_PIN_LD8__LD8, | |
127 | MX31_PIN_LD9__LD9, | |
128 | MX31_PIN_LD10__LD10, | |
129 | MX31_PIN_LD11__LD11, | |
130 | MX31_PIN_LD12__LD12, | |
131 | MX31_PIN_LD13__LD13, | |
132 | MX31_PIN_LD14__LD14, | |
133 | MX31_PIN_LD15__LD15, | |
134 | MX31_PIN_LD16__LD16, | |
135 | MX31_PIN_LD17__LD17, | |
136 | MX31_PIN_VSYNC3__VSYNC3, | |
137 | MX31_PIN_HSYNC__HSYNC, | |
138 | MX31_PIN_FPSHIFT__FPSHIFT, | |
139 | MX31_PIN_CONTRAST__CONTRAST, | |
164f7b52 AP |
140 | /* CSI */ |
141 | MX31_PIN_CSI_D6__CSI_D6, | |
142 | MX31_PIN_CSI_D7__CSI_D7, | |
143 | MX31_PIN_CSI_D8__CSI_D8, | |
144 | MX31_PIN_CSI_D9__CSI_D9, | |
145 | MX31_PIN_CSI_D10__CSI_D10, | |
146 | MX31_PIN_CSI_D11__CSI_D11, | |
147 | MX31_PIN_CSI_D12__CSI_D12, | |
148 | MX31_PIN_CSI_D13__CSI_D13, | |
149 | MX31_PIN_CSI_D14__CSI_D14, | |
150 | MX31_PIN_CSI_D15__CSI_D15, | |
151 | MX31_PIN_CSI_HSYNC__CSI_HSYNC, | |
152 | MX31_PIN_CSI_MCLK__CSI_MCLK, | |
153 | MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, | |
154 | MX31_PIN_CSI_VSYNC__CSI_VSYNC, | |
155 | MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */ | |
156 | IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */ | |
5fb86e5d PR |
157 | /* SSI */ |
158 | MX31_PIN_STXD4__STXD4, | |
159 | MX31_PIN_SRXD4__SRXD4, | |
160 | MX31_PIN_SCK4__SCK4, | |
161 | MX31_PIN_SFS4__SFS4, | |
164f7b52 AP |
162 | }; |
163 | ||
164 | /* | |
165 | * Camera support | |
166 | */ | |
167 | static phys_addr_t mx3_camera_base __initdata; | |
168 | #define MX31_3DS_CAMERA_BUF_SIZE SZ_8M | |
169 | ||
170 | #define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5) | |
171 | #define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1) | |
172 | ||
173 | static struct gpio mx31_3ds_camera_gpios[] = { | |
174 | { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" }, | |
175 | { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" }, | |
176 | }; | |
177 | ||
afa77ef3 UKK |
178 | static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = { |
179 | .flags = MX3_CAMERA_DATAWIDTH_10, | |
180 | .mclk_10khz = 2600, | |
181 | }; | |
182 | ||
183 | static int __init mx31_3ds_init_camera(void) | |
164f7b52 | 184 | { |
afa77ef3 UKK |
185 | int dma, ret = -ENOMEM; |
186 | struct platform_device *pdev = | |
187 | imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata); | |
188 | ||
189 | if (IS_ERR(pdev)) | |
190 | return PTR_ERR(pdev); | |
164f7b52 AP |
191 | |
192 | if (!mx3_camera_base) | |
afa77ef3 | 193 | goto err; |
164f7b52 | 194 | |
afa77ef3 | 195 | dma = dma_declare_coherent_memory(&pdev->dev, |
164f7b52 AP |
196 | mx3_camera_base, mx3_camera_base, |
197 | MX31_3DS_CAMERA_BUF_SIZE, | |
198 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); | |
199 | ||
200 | if (!(dma & DMA_MEMORY_MAP)) | |
afa77ef3 | 201 | goto err; |
164f7b52 | 202 | |
afa77ef3 UKK |
203 | ret = platform_device_add(pdev); |
204 | if (ret) | |
205 | err: | |
206 | platform_device_put(pdev); | |
207 | ||
208 | return ret; | |
164f7b52 AP |
209 | } |
210 | ||
211 | static int mx31_3ds_camera_power(struct device *dev, int on) | |
212 | { | |
213 | /* enable or disable the camera */ | |
214 | pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE"); | |
215 | gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1); | |
216 | ||
217 | if (!on) | |
218 | goto out; | |
219 | ||
220 | /* If enabled, give a reset impulse */ | |
221 | gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0); | |
222 | msleep(20); | |
223 | gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1); | |
224 | msleep(100); | |
225 | ||
226 | out: | |
227 | return 0; | |
228 | } | |
229 | ||
230 | static struct i2c_board_info mx31_3ds_i2c_camera = { | |
231 | I2C_BOARD_INFO("ov2640", 0x30), | |
232 | }; | |
233 | ||
234 | static struct regulator_bulk_data mx31_3ds_camera_regs[] = { | |
235 | { .supply = "cmos_vcore" }, | |
236 | { .supply = "cmos_2v8" }, | |
237 | }; | |
238 | ||
239 | static struct soc_camera_link iclink_ov2640 = { | |
240 | .bus_id = 0, | |
241 | .board_info = &mx31_3ds_i2c_camera, | |
242 | .i2c_adapter_id = 0, | |
243 | .power = mx31_3ds_camera_power, | |
244 | .regulators = mx31_3ds_camera_regs, | |
245 | .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs), | |
246 | }; | |
247 | ||
248 | static struct platform_device mx31_3ds_ov2640 = { | |
249 | .name = "soc-camera-pdrv", | |
250 | .id = 0, | |
251 | .dev = { | |
252 | .platform_data = &iclink_ov2640, | |
253 | }, | |
254 | }; | |
255 | ||
e42010e0 AP |
256 | /* |
257 | * FB support | |
258 | */ | |
259 | static const struct fb_videomode fb_modedb[] = { | |
260 | { /* 480x640 @ 60 Hz */ | |
261 | .name = "Epson-VGA", | |
262 | .refresh = 60, | |
263 | .xres = 480, | |
264 | .yres = 640, | |
265 | .pixclock = 41701, | |
266 | .left_margin = 20, | |
267 | .right_margin = 41, | |
268 | .upper_margin = 10, | |
269 | .lower_margin = 5, | |
270 | .hsync_len = 20, | |
271 | .vsync_len = 10, | |
272 | .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, | |
273 | .vmode = FB_VMODE_NONINTERLACED, | |
274 | .flag = 0, | |
275 | }, | |
276 | }; | |
277 | ||
afa77ef3 | 278 | static struct mx3fb_platform_data mx3fb_pdata __initdata = { |
e42010e0 AP |
279 | .name = "Epson-VGA", |
280 | .mode = fb_modedb, | |
281 | .num_modes = ARRAY_SIZE(fb_modedb), | |
282 | }; | |
283 | ||
284 | /* LCD */ | |
285 | static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = { | |
286 | .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1), | |
287 | .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS), | |
0ce88b34 AP |
288 | }; |
289 | ||
290 | /* | |
291 | * Support for SD card slot in personality board | |
292 | */ | |
293 | #define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) | |
294 | #define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) | |
295 | ||
296 | static struct gpio mx31_3ds_sdhc1_gpios[] = { | |
297 | { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" }, | |
298 | { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" }, | |
299 | }; | |
300 | ||
301 | static int mx31_3ds_sdhc1_init(struct device *dev, | |
302 | irq_handler_t detect_irq, | |
303 | void *data) | |
304 | { | |
305 | int ret; | |
306 | ||
307 | ret = gpio_request_array(mx31_3ds_sdhc1_gpios, | |
308 | ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); | |
309 | if (ret) { | |
75fd32b8 | 310 | pr_warn("Unable to request the SD/MMC GPIOs.\n"); |
0ce88b34 AP |
311 | return ret; |
312 | } | |
313 | ||
ed175343 | 314 | ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), |
4c1dd3e5 | 315 | detect_irq, |
0ce88b34 AP |
316 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, |
317 | "sdhc1-detect", data); | |
318 | if (ret) { | |
75fd32b8 | 319 | pr_warn("Unable to request the SD/MMC card-detect IRQ.\n"); |
0ce88b34 AP |
320 | goto gpio_free; |
321 | } | |
322 | ||
323 | return 0; | |
324 | ||
325 | gpio_free: | |
326 | gpio_free_array(mx31_3ds_sdhc1_gpios, | |
327 | ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); | |
328 | return ret; | |
329 | } | |
330 | ||
331 | static void mx31_3ds_sdhc1_exit(struct device *dev, void *data) | |
332 | { | |
ed175343 | 333 | free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data); |
0ce88b34 AP |
334 | gpio_free_array(mx31_3ds_sdhc1_gpios, |
335 | ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); | |
336 | } | |
337 | ||
338 | static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd) | |
339 | { | |
340 | /* | |
341 | * While the voltage stuff is done by the driver, activate the | |
342 | * Buffer Enable Pin only if there is a card in slot to fix the card | |
343 | * voltage issue caused by bi-directional chip TXB0108 on 3Stack. | |
344 | * Done here because at this stage we have for sure a debounced value | |
345 | * of the presence of the card, showed by the value of vdd. | |
346 | * 7 == ilog2(MMC_VDD_165_195) | |
347 | */ | |
348 | if (vdd > 7) | |
349 | gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1); | |
350 | else | |
351 | gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0); | |
352 | } | |
353 | ||
354 | static struct imxmmc_platform_data sdhc1_pdata = { | |
355 | .init = mx31_3ds_sdhc1_init, | |
356 | .exit = mx31_3ds_sdhc1_exit, | |
357 | .setpower = mx31_3ds_sdhc1_setpower, | |
54c1f636 AP |
358 | }; |
359 | ||
360 | /* | |
361 | * Matrix keyboard | |
362 | */ | |
363 | ||
364 | static const uint32_t mx31_3ds_keymap[] = { | |
365 | KEY(0, 0, KEY_UP), | |
366 | KEY(0, 1, KEY_DOWN), | |
367 | KEY(1, 0, KEY_RIGHT), | |
368 | KEY(1, 1, KEY_LEFT), | |
369 | KEY(1, 2, KEY_ENTER), | |
370 | KEY(2, 0, KEY_F6), | |
371 | KEY(2, 1, KEY_F8), | |
372 | KEY(2, 2, KEY_F9), | |
373 | KEY(2, 3, KEY_F10), | |
374 | }; | |
375 | ||
d690b4c4 | 376 | static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = { |
54c1f636 AP |
377 | .keymap = mx31_3ds_keymap, |
378 | .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), | |
ae7a3f13 AP |
379 | }; |
380 | ||
381 | /* Regulators */ | |
382 | static struct regulator_init_data pwgtx_init = { | |
383 | .constraints = { | |
384 | .boot_on = 1, | |
385 | .always_on = 1, | |
386 | }, | |
387 | }; | |
388 | ||
0d95b75e FE |
389 | static struct regulator_init_data gpo_init = { |
390 | .constraints = { | |
391 | .boot_on = 1, | |
392 | .always_on = 1, | |
393 | } | |
394 | }; | |
395 | ||
0ce88b34 | 396 | static struct regulator_consumer_supply vmmc2_consumers[] = { |
7f917a8d | 397 | REGULATOR_SUPPLY("vmmc", "imx31-mmc.0"), |
0ce88b34 AP |
398 | }; |
399 | ||
400 | static struct regulator_init_data vmmc2_init = { | |
401 | .constraints = { | |
402 | .min_uV = 3000000, | |
403 | .max_uV = 3000000, | |
404 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
405 | REGULATOR_CHANGE_STATUS, | |
406 | }, | |
407 | .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers), | |
408 | .consumer_supplies = vmmc2_consumers, | |
409 | }; | |
410 | ||
e42010e0 | 411 | static struct regulator_consumer_supply vmmc1_consumers[] = { |
0556dc34 | 412 | REGULATOR_SUPPLY("vcore", "spi0.0"), |
164f7b52 | 413 | REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"), |
e42010e0 AP |
414 | }; |
415 | ||
416 | static struct regulator_init_data vmmc1_init = { | |
417 | .constraints = { | |
418 | .min_uV = 2800000, | |
419 | .max_uV = 2800000, | |
420 | .apply_uV = 1, | |
421 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
422 | REGULATOR_CHANGE_STATUS, | |
423 | }, | |
424 | .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), | |
425 | .consumer_supplies = vmmc1_consumers, | |
426 | }; | |
427 | ||
428 | static struct regulator_consumer_supply vgen_consumers[] = { | |
0556dc34 | 429 | REGULATOR_SUPPLY("vdd", "spi0.0"), |
e42010e0 AP |
430 | }; |
431 | ||
432 | static struct regulator_init_data vgen_init = { | |
433 | .constraints = { | |
434 | .min_uV = 1800000, | |
435 | .max_uV = 1800000, | |
436 | .apply_uV = 1, | |
437 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
438 | REGULATOR_CHANGE_STATUS, | |
439 | }, | |
440 | .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), | |
441 | .consumer_supplies = vgen_consumers, | |
442 | }; | |
443 | ||
164f7b52 AP |
444 | static struct regulator_consumer_supply vvib_consumers[] = { |
445 | REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"), | |
446 | }; | |
447 | ||
448 | static struct regulator_init_data vvib_init = { | |
449 | .constraints = { | |
450 | .min_uV = 1300000, | |
451 | .max_uV = 1300000, | |
452 | .apply_uV = 1, | |
453 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
454 | REGULATOR_CHANGE_STATUS, | |
455 | }, | |
456 | .num_consumer_supplies = ARRAY_SIZE(vvib_consumers), | |
457 | .consumer_supplies = vvib_consumers, | |
458 | }; | |
459 | ||
5836372e | 460 | static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { |
ae7a3f13 | 461 | { |
57c78e35 | 462 | .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ |
ae7a3f13 AP |
463 | .init_data = &pwgtx_init, |
464 | }, { | |
57c78e35 | 465 | .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */ |
ae7a3f13 | 466 | .init_data = &pwgtx_init, |
0d95b75e FE |
467 | }, { |
468 | ||
c97b7393 | 469 | .id = MC13783_REG_GPO1, /* Turn on 1.8V */ |
0d95b75e FE |
470 | .init_data = &gpo_init, |
471 | }, { | |
c97b7393 | 472 | .id = MC13783_REG_GPO3, /* Turn on 3.3V */ |
0d95b75e | 473 | .init_data = &gpo_init, |
0ce88b34 AP |
474 | }, { |
475 | .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */ | |
476 | .init_data = &vmmc2_init, | |
e42010e0 AP |
477 | }, { |
478 | .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */ | |
479 | .init_data = &vmmc1_init, | |
480 | }, { | |
481 | .id = MC13783_REG_VGEN, /* Power LCD */ | |
482 | .init_data = &vgen_init, | |
164f7b52 AP |
483 | }, { |
484 | .id = MC13783_REG_VVIB, /* Power CMOS */ | |
485 | .init_data = &vvib_init, | |
ae7a3f13 AP |
486 | }, |
487 | }; | |
488 | ||
489 | /* MC13783 */ | |
5fb86e5d PR |
490 | static struct mc13xxx_codec_platform_data mx31_3ds_codec = { |
491 | .dac_ssi_port = MC13783_SSI1_PORT, | |
492 | .adc_ssi_port = MC13783_SSI1_PORT, | |
493 | }; | |
494 | ||
4ec1b54c AS |
495 | static struct mc13xxx_platform_data mc13783_pdata = { |
496 | .regulators = { | |
497 | .regulators = mx31_3ds_regulators, | |
498 | .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), | |
499 | }, | |
5fb86e5d PR |
500 | .codec = &mx31_3ds_codec, |
501 | .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC, | |
502 | ||
503 | }; | |
504 | ||
505 | static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = { | |
506 | .flags = IMX_SSI_DMA | IMX_SSI_NET, | |
a1ac4424 AP |
507 | }; |
508 | ||
509 | /* SPI */ | |
e42010e0 AP |
510 | static int spi0_internal_chipselect[] = { |
511 | MXC_SPI_CS(2), | |
512 | }; | |
513 | ||
514 | static const struct spi_imx_master spi0_pdata __initconst = { | |
515 | .chipselect = spi0_internal_chipselect, | |
516 | .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect), | |
517 | }; | |
518 | ||
a1ac4424 AP |
519 | static int spi1_internal_chipselect[] = { |
520 | MXC_SPI_CS(0), | |
521 | MXC_SPI_CS(2), | |
522 | }; | |
523 | ||
06606ff1 | 524 | static const struct spi_imx_master spi1_pdata __initconst = { |
a1ac4424 AP |
525 | .chipselect = spi1_internal_chipselect, |
526 | .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect), | |
63d97667 VL |
527 | }; |
528 | ||
ae7a3f13 AP |
529 | static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { |
530 | { | |
531 | .modalias = "mc13783", | |
532 | .max_speed_hz = 1000000, | |
533 | .bus_num = 1, | |
534 | .chip_select = 1, /* SS2 */ | |
535 | .platform_data = &mc13783_pdata, | |
ed175343 | 536 | /* irq number is run-time assigned */ |
ae7a3f13 | 537 | .mode = SPI_CS_HIGH, |
e42010e0 AP |
538 | }, { |
539 | .modalias = "l4f00242t03", | |
540 | .max_speed_hz = 5000000, | |
541 | .bus_num = 0, | |
542 | .chip_select = 0, /* SS2 */ | |
543 | .platform_data = &mx31_3ds_l4f00242t03_pdata, | |
ae7a3f13 AP |
544 | }, |
545 | }; | |
546 | ||
a1b67b95 AP |
547 | /* |
548 | * NAND Flash | |
549 | */ | |
a2ceeef5 UKK |
550 | static const struct mxc_nand_platform_data |
551 | mx31_3ds_nand_board_info __initconst = { | |
a1b67b95 AP |
552 | .width = 1, |
553 | .hw_ecc = 1, | |
5328ecbb | 554 | #ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT |
a1b67b95 AP |
555 | .flash_bbt = 1, |
556 | #endif | |
557 | }; | |
558 | ||
a2ef4562 ML |
559 | /* |
560 | * USB OTG | |
561 | */ | |
562 | ||
563 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ | |
564 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | |
565 | ||
566 | #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) | |
0d95b75e | 567 | #define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP) |
a2ef4562 | 568 | |
41f63475 | 569 | static int mx31_3ds_usbotg_init(void) |
a2ef4562 | 570 | { |
41f63475 FE |
571 | int err; |
572 | ||
a2ef4562 ML |
573 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); |
574 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); | |
575 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); | |
576 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); | |
577 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); | |
578 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); | |
579 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); | |
580 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); | |
581 | mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); | |
582 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); | |
583 | mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); | |
584 | mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); | |
585 | ||
41f63475 FE |
586 | err = gpio_request(USBOTG_RST_B, "otgusb-reset"); |
587 | if (err) { | |
588 | pr_err("Failed to request the USB OTG reset gpio\n"); | |
589 | return err; | |
590 | } | |
591 | ||
592 | err = gpio_direction_output(USBOTG_RST_B, 0); | |
593 | if (err) { | |
594 | pr_err("Failed to drive the USB OTG reset gpio\n"); | |
595 | goto usbotg_free_reset; | |
596 | } | |
597 | ||
a2ef4562 ML |
598 | mdelay(1); |
599 | gpio_set_value(USBOTG_RST_B, 1); | |
41f63475 FE |
600 | return 0; |
601 | ||
602 | usbotg_free_reset: | |
603 | gpio_free(USBOTG_RST_B); | |
604 | return err; | |
a2ef4562 ML |
605 | } |
606 | ||
4bd597b6 SH |
607 | static int mx31_3ds_otg_init(struct platform_device *pdev) |
608 | { | |
609 | return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); | |
610 | } | |
611 | ||
612 | static int mx31_3ds_host2_init(struct platform_device *pdev) | |
0d95b75e FE |
613 | { |
614 | int err; | |
615 | ||
616 | mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); | |
617 | mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); | |
618 | mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); | |
619 | mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); | |
620 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); | |
621 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); | |
622 | mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG); | |
623 | mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG); | |
624 | mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG); | |
625 | mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG); | |
626 | mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG); | |
627 | mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG); | |
628 | ||
629 | err = gpio_request(USBH2_RST_B, "usbh2-reset"); | |
630 | if (err) { | |
631 | pr_err("Failed to request the USB Host 2 reset gpio\n"); | |
632 | return err; | |
633 | } | |
634 | ||
635 | err = gpio_direction_output(USBH2_RST_B, 0); | |
636 | if (err) { | |
637 | pr_err("Failed to drive the USB Host 2 reset gpio\n"); | |
638 | goto usbotg_free_reset; | |
639 | } | |
640 | ||
641 | mdelay(1); | |
642 | gpio_set_value(USBH2_RST_B, 1); | |
4bd597b6 SH |
643 | |
644 | mdelay(10); | |
645 | ||
646 | return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); | |
0d95b75e FE |
647 | |
648 | usbotg_free_reset: | |
649 | gpio_free(USBH2_RST_B); | |
650 | return err; | |
651 | } | |
652 | ||
1c50e672 | 653 | static struct mxc_usbh_platform_data otg_pdata __initdata = { |
4bd597b6 | 654 | .init = mx31_3ds_otg_init, |
1c50e672 | 655 | .portsc = MXC_EHCI_MODE_ULPI, |
1c50e672 | 656 | }; |
0d95b75e FE |
657 | |
658 | static struct mxc_usbh_platform_data usbh2_pdata __initdata = { | |
659 | .init = mx31_3ds_host2_init, | |
660 | .portsc = MXC_EHCI_MODE_ULPI, | |
0d95b75e | 661 | }; |
1c50e672 | 662 | |
9e1dde33 | 663 | static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { |
a2ef4562 ML |
664 | .operating_mode = FSL_USB2_DR_DEVICE, |
665 | .phy_mode = FSL_USB2_PHY_ULPI, | |
666 | }; | |
667 | ||
33a264dd | 668 | static bool otg_mode_host __initdata; |
1c50e672 FE |
669 | |
670 | static int __init mx31_3ds_otg_mode(char *options) | |
671 | { | |
672 | if (!strcmp(options, "host")) | |
33a264dd | 673 | otg_mode_host = true; |
1c50e672 | 674 | else if (!strcmp(options, "device")) |
33a264dd | 675 | otg_mode_host = false; |
1c50e672 FE |
676 | else |
677 | pr_info("otg_mode neither \"host\" nor \"device\". " | |
678 | "Defaulting to device\n"); | |
33a264dd | 679 | return 1; |
1c50e672 FE |
680 | } |
681 | __setup("otg_mode=", mx31_3ds_otg_mode); | |
682 | ||
16cf5c41 | 683 | static const struct imxuart_platform_data uart_pdata __initconst = { |
153fa1d8 ML |
684 | .flags = IMXUART_HAVE_RTSCTS, |
685 | }; | |
1553a1ec | 686 | |
3d943024 FE |
687 | static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = { |
688 | .bitrate = 100000, | |
689 | }; | |
690 | ||
164f7b52 AP |
691 | static struct platform_device *devices[] __initdata = { |
692 | &mx31_3ds_ov2640, | |
693 | }; | |
694 | ||
e134fb2b | 695 | static void __init mx31_3ds_init(void) |
1553a1ec | 696 | { |
164f7b52 AP |
697 | int ret; |
698 | ||
b78d8e59 SG |
699 | imx31_soc_init(); |
700 | ||
b2a08e3e FE |
701 | /* Configure SPI1 IOMUX */ |
702 | mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true); | |
703 | ||
11a332ad AP |
704 | mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), |
705 | "mx31_3ds"); | |
153fa1d8 | 706 | |
16cf5c41 | 707 | imx31_add_imx_uart0(&uart_pdata); |
a2ceeef5 | 708 | imx31_add_mxc_nand(&mx31_3ds_nand_board_info); |
ae7a3f13 | 709 | |
4a74bddc | 710 | imx31_add_spi_imx1(&spi1_pdata); |
ed175343 | 711 | mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); |
ae7a3f13 AP |
712 | spi_register_board_info(mx31_3ds_spi_devs, |
713 | ARRAY_SIZE(mx31_3ds_spi_devs)); | |
135cad36 | 714 | |
164f7b52 AP |
715 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
716 | ||
d690b4c4 | 717 | imx31_add_imx_keypad(&mx31_3ds_keymap_data); |
54c1f636 | 718 | |
a2ef4562 | 719 | mx31_3ds_usbotg_init(); |
1c50e672 | 720 | if (otg_mode_host) { |
48f6b099 SH |
721 | otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | |
722 | ULPI_OTG_DRVVBUS_EXT); | |
723 | if (otg_pdata.otg) | |
724 | imx31_add_mxc_ehci_otg(&otg_pdata); | |
1c50e672 | 725 | } |
48f6b099 SH |
726 | usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | |
727 | ULPI_OTG_DRVVBUS_EXT); | |
728 | if (usbh2_pdata.otg) | |
729 | imx31_add_mxc_ehci_hs(2, &usbh2_pdata); | |
730 | ||
1c50e672 FE |
731 | if (!otg_mode_host) |
732 | imx31_add_fsl_usb2_udc(&usbotg_pdata); | |
a2ef4562 | 733 | |
ed4a7fb0 | 734 | if (mxc_expio_init(MX31_CS5_BASE_ADDR, IOMUX_TO_GPIO(MX31_PIN_GPIO1_1))) |
b8be7b9a RP |
735 | printk(KERN_WARNING "Init of the debug board failed, all " |
736 | "devices on the debug board are unusable.\n"); | |
bec31a85 | 737 | imx31_add_imx2_wdt(); |
3d943024 | 738 | imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); |
0ce88b34 | 739 | imx31_add_mxc_mmc(0, &sdhc1_pdata); |
e42010e0 AP |
740 | |
741 | imx31_add_spi_imx0(&spi0_pdata); | |
88289c80 | 742 | imx31_add_ipu_core(); |
afa77ef3 | 743 | imx31_add_mx3_sdc_fb(&mx3fb_pdata); |
164f7b52 AP |
744 | |
745 | /* CSI */ | |
746 | /* Camera power: default - off */ | |
747 | ret = gpio_request_array(mx31_3ds_camera_gpios, | |
748 | ARRAY_SIZE(mx31_3ds_camera_gpios)); | |
749 | if (ret) { | |
750 | pr_err("Failed to request camera gpios"); | |
751 | iclink_ov2640.power = NULL; | |
752 | } | |
753 | ||
afa77ef3 | 754 | mx31_3ds_init_camera(); |
5fb86e5d PR |
755 | |
756 | imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata); | |
757 | ||
758 | imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0); | |
1553a1ec FE |
759 | } |
760 | ||
11a332ad | 761 | static void __init mx31_3ds_timer_init(void) |
1553a1ec | 762 | { |
30c730f8 | 763 | mx31_clocks_init(26000000); |
1553a1ec FE |
764 | } |
765 | ||
164f7b52 AP |
766 | static void __init mx31_3ds_reserve(void) |
767 | { | |
768 | /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ | |
716a3dc2 | 769 | mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE, |
164f7b52 | 770 | MX31_3DS_CAMERA_BUF_SIZE); |
164f7b52 AP |
771 | } |
772 | ||
1553a1ec FE |
773 | MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") |
774 | /* Maintainer: Freescale Semiconductor, Inc. */ | |
dc8f1907 | 775 | .atag_offset = 0x100, |
97976e22 UKK |
776 | .map_io = mx31_map_io, |
777 | .init_early = imx31_init_early, | |
778 | .init_irq = mx31_init_irq, | |
6bb27d73 | 779 | .init_time = mx31_3ds_timer_init, |
e134fb2b | 780 | .init_machine = mx31_3ds_init, |
164f7b52 | 781 | .reserve = mx31_3ds_reserve, |
65ea7884 | 782 | .restart = mxc_restart, |
1553a1ec | 783 | MACHINE_END |