[linux-2.6-block.git] / arch / arm / mach-imx / iomux-imx31.c

/*
 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
 * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/kernel.h>

#include "hardware.h"
#include "iomux-mx3.h"

/*
 * IOMUX register (base) addresses
 */
#define IOMUX_BASE	MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
#define IOMUXINT_OBS1	(IOMUX_BASE + 0x000)
#define IOMUXINT_OBS2	(IOMUX_BASE + 0x004)
#define IOMUXGPR	(IOMUX_BASE + 0x008)
#define IOMUXSW_MUX_CTL	(IOMUX_BASE + 0x00C)
#define IOMUXSW_PAD_CTL	(IOMUX_BASE + 0x154)

static DEFINE_SPINLOCK(gpio_mux_lock);

#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)

static DECLARE_BITMAP(mxc_pin_alloc_map, NB_PORTS * 32);
/*
 * set the mode for a IOMUX pin.
 */
void mxc_iomux_mode(unsigned int pin_mode)
{
	u32 field;
	u32 l;
	u32 mode;
	void __iomem *reg;

	reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
	field = pin_mode & 0x3;
	mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;

	spin_lock(&gpio_mux_lock);

	l = imx_readl(reg);
	l &= ~(0xff << (field * 8));
	l |= mode << (field * 8);
	imx_writel(l, reg);

	spin_unlock(&gpio_mux_lock);
}

/*
 * This function configures the pad value for a IOMUX pin.
 */
void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
{
	u32 field, l;
	void __iomem *reg;

	pin &= IOMUX_PADNUM_MASK;
	reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
	field = (pin + 2) % 3;

	pr_debug("%s: reg offset = 0x%x, field = %d\n",
			__func__, (pin + 2) / 3, field);

	spin_lock(&gpio_mux_lock);

	l = imx_readl(reg);
	l &= ~(0x1ff << (field * 10));
	l |= config << (field * 10);
	imx_writel(l, reg);

	spin_unlock(&gpio_mux_lock);
}

/*
 * allocs a single pin:
 * 	- reserves the pin so that it is not claimed by another driver
 * 	- setups the iomux according to the configuration
 */
int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
{
	unsigned pad = pin & IOMUX_PADNUM_MASK;

	if (pad >= (PIN_MAX + 1)) {
		printk(KERN_ERR "mxc_iomux: Attempt to request nonexistent pin %u for \"%s\"\n",
			pad, label ? label : "?");
		return -EINVAL;
	}

	if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
		printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
			pad, label ? label : "?");
		return -EBUSY;
	}
	mxc_iomux_mode(pin);

	return 0;
}

int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
		const char *label)
{
	const unsigned int *p = pin_list;
	int i;
	int ret = -EINVAL;

	for (i = 0; i < count; i++) {
		ret = mxc_iomux_alloc_pin(*p, label);
		if (ret)
			goto setup_error;
		p++;
	}
	return 0;

setup_error:
	mxc_iomux_release_multiple_pins(pin_list, i);
	return ret;
}

void mxc_iomux_release_pin(unsigned int pin)
{
	unsigned pad = pin & IOMUX_PADNUM_MASK;

	if (pad < (PIN_MAX + 1))
		clear_bit(pad, mxc_pin_alloc_map);
}

void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
{
	const unsigned int *p = pin_list;
	int i;

	for (i = 0; i < count; i++) {
		mxc_iomux_release_pin(*p);
		p++;
	}
}

/*
 * This function enables/disables the general purpose function for a particular
 * signal.
 */
void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
{
	u32 l;

	spin_lock(&gpio_mux_lock);
	l = imx_readl(IOMUXGPR);
	if (en)
		l |= gp;
	else
		l &= ~gp;

	imx_writel(l, IOMUXGPR);
	spin_unlock(&gpio_mux_lock);
}
Commit	Line	Data
90292ea6 SH	1	/*
	2	* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
b7222631	4	* Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
90292ea6 SH	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	18	* MA 02110-1301, USA.
	19	*/
2f8163ba	20	#include <linux/gpio.h>
90292ea6 SH	21	#include <linux/module.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/io.h>
b7222631	24	#include <linux/kernel.h>
267dd34c	25
50f2de61	26	#include "hardware.h"
267dd34c	27	#include "iomux-mx3.h"
90292ea6 SH	28
	29	/*
	30	* IOMUX register (base) addresses
	31	*/
1273e768	32	#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
90292ea6 SH	33	#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
	34	#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
	35	#define IOMUXGPR (IOMUX_BASE + 0x008)
	36	#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
	37	#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
	38
	39	static DEFINE_SPINLOCK(gpio_mux_lock);
	40
	41	#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
b7222631	42
f6d47502	43	static DECLARE_BITMAP(mxc_pin_alloc_map, NB_PORTS * 32);
90292ea6 SH	44	/*
	45	* set the mode for a IOMUX pin.
	46	*/
c3008735	47	void mxc_iomux_mode(unsigned int pin_mode)
90292ea6	48	{
c3008735 DV	49	u32 field;
	50	u32 l;
	51	u32 mode;
defa8c30	52	void __iomem *reg;
90292ea6 SH	53
	54	reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
	55	field = pin_mode & 0x3;
	56	mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
	57
90292ea6 SH	58	spin_lock(&gpio_mux_lock);
90292ea6 SH	59
c553138f	60	l = imx_readl(reg);
90292ea6 SH	61	l &= ~(0xff << (field * 8));
90292ea6 SH	62	l \|= mode << (field * 8);
c553138f	63	imx_writel(l, reg);
90292ea6 SH	64
90292ea6 SH	65	spin_unlock(&gpio_mux_lock);
90292ea6	66	}
90292ea6 SH	67
	68	/*
	69	* This function configures the pad value for a IOMUX pin.
	70	*/
	71	void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
	72	{
defa8c30 LF	73	u32 field, l;
defa8c30 LF	74	void __iomem *reg;
90292ea6	75
4a7b98d7 GL	76	pin &= IOMUX_PADNUM_MASK;
4a7b98d7 GL	77	reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
90292ea6 SH	78	field = (pin + 2) % 3;
90292ea6 SH	79
4a7b98d7	80	pr_debug("%s: reg offset = 0x%x, field = %d\n",
90292ea6 SH	81	__func__, (pin + 2) / 3, field);
	82
	83	spin_lock(&gpio_mux_lock);
	84
c553138f	85	l = imx_readl(reg);
4a7b98d7 GL	86	l &= ~(0x1ff << (field * 10));
4a7b98d7 GL	87	l \|= config << (field * 10);
c553138f	88	imx_writel(l, reg);
90292ea6 SH	89
	90	spin_unlock(&gpio_mux_lock);
	91	}
90292ea6	92
b7222631	93	/*
ef754d63	94	* allocs a single pin:
b7222631 VL	95	* - reserves the pin so that it is not claimed by another driver
b7222631 VL	96	* - setups the iomux according to the configuration
b7222631	97	*/
10a3c45c	98	int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
b7222631 VL	99	{
b7222631 VL	100	unsigned pad = pin & IOMUX_PADNUM_MASK;
b7222631 VL	101
b7222631 VL	102	if (pad >= (PIN_MAX + 1)) {
aa9fff5d	103	printk(KERN_ERR "mxc_iomux: Attempt to request nonexistent pin %u for \"%s\"\n",
b7222631 VL	104	pad, label ? label : "?");
	105	return -EINVAL;
	106	}
	107
	108	if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
	109	printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
	110	pad, label ? label : "?");
ef754d63	111	return -EBUSY;
b7222631 VL	112	}
	113	mxc_iomux_mode(pin);
	114
b7222631 VL	115	return 0;
b7222631 VL	116	}
b7222631	117
10a3c45c	118	int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
b7222631 VL	119	const char *label)
b7222631 VL	120	{
10a3c45c	121	const unsigned int *p = pin_list;
b7222631 VL	122	int i;
	123	int ret = -EINVAL;
	124
	125	for (i = 0; i < count; i++) {
ef754d63 VL	126	ret = mxc_iomux_alloc_pin(*p, label);
ef754d63 VL	127	if (ret)
b7222631 VL	128	goto setup_error;
	129	p++;
	130	}
	131	return 0;
	132
	133	setup_error:
	134	mxc_iomux_release_multiple_pins(pin_list, i);
	135	return ret;
	136	}
b7222631	137
10a3c45c	138	void mxc_iomux_release_pin(unsigned int pin)
b7222631 VL	139	{
b7222631 VL	140	unsigned pad = pin & IOMUX_PADNUM_MASK;
b7222631 VL	141
	142	if (pad < (PIN_MAX + 1))
	143	clear_bit(pad, mxc_pin_alloc_map);
b7222631	144	}
b7222631	145
10a3c45c	146	void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
b7222631	147	{
10a3c45c	148	const unsigned int *p = pin_list;
b7222631 VL	149	int i;
	150
	151	for (i = 0; i < count; i++) {
	152	mxc_iomux_release_pin(*p);
	153	p++;
	154	}
	155	}
b7222631	156
90292ea6 SH	157	/*
	158	* This function enables/disables the general purpose function for a particular
	159	* signal.
	160	*/
	161	void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
	162	{
	163	u32 l;
	164
	165	spin_lock(&gpio_mux_lock);
c553138f	166	l = imx_readl(IOMUXGPR);
90292ea6 SH	167	if (en)
	168	l \|= gp;
	169	else
	170	l &= ~gp;
	171
c553138f	172	imx_writel(l, IOMUXGPR);
90292ea6 SH	173	spin_unlock(&gpio_mux_lock);
90292ea6 SH	174	}