[linux-2.6-block.git] / arch / arm / mach-imx / gpc.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
#include "hardware.h"

#define GPC_CNTR		0x000
#define GPC_IMR1		0x008
#define GPC_PGC_GPU_PDN		0x260
#define GPC_PGC_GPU_PUPSCR	0x264
#define GPC_PGC_GPU_PDNSCR	0x268
#define GPC_PGC_CPU_PDN		0x2a0
#define GPC_PGC_CPU_PUPSCR	0x2a4
#define GPC_PGC_CPU_PDNSCR	0x2a8
#define GPC_PGC_SW2ISO_SHIFT	0x8
#define GPC_PGC_SW_SHIFT	0x0

#define IMR_NUM			4

#define GPU_VPU_PUP_REQ		BIT(1)
#define GPU_VPU_PDN_REQ		BIT(0)

#define GPC_CLK_MAX		6

struct pu_domain {
	struct generic_pm_domain base;
	struct regulator *reg;
	struct clk *clk[GPC_CLK_MAX];
	int num_clks;
};

static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];

void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
{
	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
}

void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
{
	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
}

void imx_gpc_set_arm_power_in_lpm(bool power_off)
{
	writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
}

void imx_gpc_pre_suspend(bool arm_power_off)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	/* Tell GPC to power off ARM core when suspend */
	if (arm_power_off)
		imx_gpc_set_arm_power_in_lpm(arm_power_off);

	for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
	}
}

void imx_gpc_post_resume(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	/* Keep ARM core powered on for other low-power modes */
	imx_gpc_set_arm_power_in_lpm(false);

	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}

static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
	unsigned int idx = d->hwirq / 32 - 1;
	u32 mask;

	/* Sanity check for SPI irq */
	if (d->hwirq < 32)
		return -EINVAL;

	mask = 1 << d->hwirq % 32;
	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
				  gpc_wake_irqs[idx] & ~mask;

	return 0;
}

void imx_gpc_mask_all(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~0, reg_imr1 + i * 4);
	}

}

void imx_gpc_restore_all(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}

void imx_gpc_hwirq_unmask(unsigned int hwirq)
{
	void __iomem *reg;
	u32 val;

	reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
	val = readl_relaxed(reg);
	val &= ~(1 << hwirq % 32);
	writel_relaxed(val, reg);
}

void imx_gpc_hwirq_mask(unsigned int hwirq)
{
	void __iomem *reg;
	u32 val;

	reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
	val = readl_relaxed(reg);
	val |= 1 << (hwirq % 32);
	writel_relaxed(val, reg);
}

static void imx_gpc_irq_unmask(struct irq_data *d)
{
	/* Sanity check for SPI irq */
	if (d->hwirq < 32)
		return;

	imx_gpc_hwirq_unmask(d->hwirq);
}

static void imx_gpc_irq_mask(struct irq_data *d)
{
	/* Sanity check for SPI irq */
	if (d->hwirq < 32)
		return;

	imx_gpc_hwirq_mask(d->hwirq);
}

void __init imx_gpc_init(void)
{
	struct device_node *np;
	int i;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
	gpc_base = of_iomap(np, 0);
	WARN_ON(!gpc_base);

	/* Initially mask all interrupts */
	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);

	/* Register GPC as the secondary interrupt controller behind GIC */
	gic_arch_extn.irq_mask = imx_gpc_irq_mask;
	gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
	gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
}

#ifdef CONFIG_PM_GENERIC_DOMAINS

static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
	int iso, iso2sw;
	u32 val;

	/* Read ISO and ISO2SW power down delays */
	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
	iso = val & 0x3f;
	iso2sw = (val >> 8) & 0x3f;

	/* Gate off PU domain when GPU/VPU when powered down */
	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);

	/* Request GPC to power down GPU/VPU */
	val = readl_relaxed(gpc_base + GPC_CNTR);
	val |= GPU_VPU_PDN_REQ;
	writel_relaxed(val, gpc_base + GPC_CNTR);

	/* Wait ISO + ISO2SW IPG clock cycles */
	ndelay((iso + iso2sw) * 1000 / 66);
}

static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);

	_imx6q_pm_pu_power_off(genpd);

	if (pu->reg)
		regulator_disable(pu->reg);

	return 0;
}

static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
{
	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
	int i, ret, sw, sw2iso;
	u32 val;

	if (pu->reg)
		ret = regulator_enable(pu->reg);
	if (pu->reg && ret) {
		pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
		return ret;
	}

	/* Enable reset clocks for all devices in the PU domain */
	for (i = 0; i < pu->num_clks; i++)
		clk_prepare_enable(pu->clk[i]);

	/* Gate off PU domain when GPU/VPU when powered down */
	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);

	/* Read ISO and ISO2SW power down delays */
	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
	sw = val & 0x3f;
	sw2iso = (val >> 8) & 0x3f;

	/* Request GPC to power up GPU/VPU */
	val = readl_relaxed(gpc_base + GPC_CNTR);
	val |= GPU_VPU_PUP_REQ;
	writel_relaxed(val, gpc_base + GPC_CNTR);

	/* Wait ISO + ISO2SW IPG clock cycles */
	ndelay((sw + sw2iso) * 1000 / 66);

	/* Disable reset clocks for all devices in the PU domain */
	for (i = 0; i < pu->num_clks; i++)
		clk_disable_unprepare(pu->clk[i]);

	return 0;
}

static struct generic_pm_domain imx6q_arm_domain = {
	.name = "ARM",
};

static struct pu_domain imx6q_pu_domain = {
	.base = {
		.name = "PU",
		.power_off = imx6q_pm_pu_power_off,
		.power_on = imx6q_pm_pu_power_on,
		.power_off_latency_ns = 25000,
		.power_on_latency_ns = 2000000,
	},
};

static struct generic_pm_domain imx6sl_display_domain = {
	.name = "DISPLAY",
};

static struct generic_pm_domain *imx_gpc_domains[] = {
	&imx6q_arm_domain,
	&imx6q_pu_domain.base,
	&imx6sl_display_domain,
};

static struct genpd_onecell_data imx_gpc_onecell_data = {
	.domains = imx_gpc_domains,
	.num_domains = ARRAY_SIZE(imx_gpc_domains),
};

static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
{
	struct clk *clk;
	bool is_off;
	int i;

	imx6q_pu_domain.reg = pu_reg;

	for (i = 0; ; i++) {
		clk = of_clk_get(dev->of_node, i);
		if (IS_ERR(clk))
			break;
		if (i >= GPC_CLK_MAX) {
			dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
			goto clk_err;
		}
		imx6q_pu_domain.clk[i] = clk;
	}
	imx6q_pu_domain.num_clks = i;

	is_off = IS_ENABLED(CONFIG_PM);
	if (is_off) {
		_imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
	} else {
		/*
		 * Enable power if compiled without CONFIG_PM in case the
		 * bootloader disabled it.
		 */
		imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
	}

	pm_genpd_init(&imx6q_pu_domain.base, NULL, is_off);
	return of_genpd_add_provider_onecell(dev->of_node,
					     &imx_gpc_onecell_data);

clk_err:
	while (i--)
		clk_put(imx6q_pu_domain.clk[i]);
	return -EINVAL;
}

#else
static inline int imx_gpc_genpd_init(struct device *dev, struct regulator *reg)
{
	return 0;
}
#endif /* CONFIG_PM_GENERIC_DOMAINS */

static int imx_gpc_probe(struct platform_device *pdev)
{
	struct regulator *pu_reg;
	int ret;

	pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
	if (PTR_ERR(pu_reg) == -ENODEV)
		pu_reg = NULL;
	if (IS_ERR(pu_reg)) {
		ret = PTR_ERR(pu_reg);
		dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
		return ret;
	}

	return imx_gpc_genpd_init(&pdev->dev, pu_reg);
}

static const struct of_device_id imx_gpc_dt_ids[] = {
	{ .compatible = "fsl,imx6q-gpc" },
	{ .compatible = "fsl,imx6sl-gpc" },
	{ }
};

static struct platform_driver imx_gpc_driver = {
	.driver = {
		.name = "imx-gpc",
		.owner = THIS_MODULE,
		.of_match_table = imx_gpc_dt_ids,
	},
	.probe = imx_gpc_probe,
};

static int __init imx_pgc_init(void)
{
	return platform_driver_register(&imx_gpc_driver);
}
subsys_initcall(imx_pgc_init);
Commit	Line	Data
9fbbe689	1	/*
263475d4	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
9fbbe689 SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
00eb60a8 PZ	13	#include <linux/clk.h>
00eb60a8 PZ	14	#include <linux/delay.h>
9fbbe689 SG	15	#include <linux/io.h>
	16	#include <linux/irq.h>
	17	#include <linux/of.h>
	18	#include <linux/of_address.h>
	19	#include <linux/of_irq.h>
00eb60a8 PZ	20	#include <linux/platform_device.h>
	21	#include <linux/pm_domain.h>
	22	#include <linux/regulator/consumer.h>
520f7bd7	23	#include <linux/irqchip/arm-gic.h>
9a67a6fd	24	#include "common.h"
00eb60a8	25	#include "hardware.h"
9fbbe689	26
00eb60a8	27	#define GPC_CNTR 0x000
9fbbe689	28	#define GPC_IMR1 0x008
00eb60a8 PZ	29	#define GPC_PGC_GPU_PDN 0x260
	30	#define GPC_PGC_GPU_PUPSCR 0x264
	31	#define GPC_PGC_GPU_PDNSCR 0x268
9fbbe689	32	#define GPC_PGC_CPU_PDN 0x2a0
05136f08 AH	33	#define GPC_PGC_CPU_PUPSCR 0x2a4
	34	#define GPC_PGC_CPU_PDNSCR 0x2a8
	35	#define GPC_PGC_SW2ISO_SHIFT 0x8
	36	#define GPC_PGC_SW_SHIFT 0x0
9fbbe689 SG	37
	38	#define IMR_NUM 4
	39
00eb60a8 PZ	40	#define GPU_VPU_PUP_REQ BIT(1)
	41	#define GPU_VPU_PDN_REQ BIT(0)
	42
	43	#define GPC_CLK_MAX 6
	44
	45	struct pu_domain {
	46	struct generic_pm_domain base;
	47	struct regulator *reg;
	48	struct clk *clk[GPC_CLK_MAX];
	49	int num_clks;
	50	};
	51
9fbbe689 SG	52	static void __iomem *gpc_base;
	53	static u32 gpc_wake_irqs[IMR_NUM];
	54	static u32 gpc_saved_imrs[IMR_NUM];
	55
05136f08 AH	56	void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
	57	{
	58	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) \|
	59	(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
	60	}
	61
	62	void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
	63	{
	64	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) \|
	65	(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
	66	}
	67
	68	void imx_gpc_set_arm_power_in_lpm(bool power_off)
	69	{
	70	writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
	71	}
	72
80c0ecdc	73	void imx_gpc_pre_suspend(bool arm_power_off)
9fbbe689 SG	74	{
	75	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	76	int i;
	77
	78	/* Tell GPC to power off ARM core when suspend */
80c0ecdc	79	if (arm_power_off)
05136f08	80	imx_gpc_set_arm_power_in_lpm(arm_power_off);
9fbbe689 SG	81
	82	for (i = 0; i < IMR_NUM; i++) {
	83	gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
	84	writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
	85	}
	86	}
	87
	88	void imx_gpc_post_resume(void)
	89	{
	90	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	91	int i;
	92
	93	/* Keep ARM core powered on for other low-power modes */
05136f08	94	imx_gpc_set_arm_power_in_lpm(false);
9fbbe689 SG	95
	96	for (i = 0; i < IMR_NUM; i++)
	97	writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
	98	}
	99
	100	static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
	101	{
e2fd06f6	102	unsigned int idx = d->hwirq / 32 - 1;
9fbbe689 SG	103	u32 mask;
	104
	105	/* Sanity check for SPI irq */
e2fd06f6	106	if (d->hwirq < 32)
9fbbe689 SG	107	return -EINVAL;
9fbbe689 SG	108
e2fd06f6	109	mask = 1 << d->hwirq % 32;
9fbbe689 SG	110	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] \| mask :
	111	gpc_wake_irqs[idx] & ~mask;
	112
	113	return 0;
	114	}
	115
263475d4 AH	116	void imx_gpc_mask_all(void)
	117	{
	118	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	119	int i;
	120
	121	for (i = 0; i < IMR_NUM; i++) {
	122	gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
	123	writel_relaxed(~0, reg_imr1 + i * 4);
	124	}
	125
	126	}
	127
	128	void imx_gpc_restore_all(void)
	129	{
	130	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	131	int i;
	132
	133	for (i = 0; i < IMR_NUM; i++)
	134	writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
	135	}
	136
65bb688a	137	void imx_gpc_hwirq_unmask(unsigned int hwirq)
9fbbe689 SG	138	{
	139	void __iomem *reg;
	140	u32 val;
	141
65bb688a	142	reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
9fbbe689	143	val = readl_relaxed(reg);
65bb688a	144	val &= ~(1 << hwirq % 32);
9fbbe689 SG	145	writel_relaxed(val, reg);
	146	}
	147
65bb688a	148	void imx_gpc_hwirq_mask(unsigned int hwirq)
9fbbe689 SG	149	{
	150	void __iomem *reg;
	151	u32 val;
	152
65bb688a MZ	153	reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
	154	val = readl_relaxed(reg);
	155	val \|= 1 << (hwirq % 32);
	156	writel_relaxed(val, reg);
	157	}
	158
	159	static void imx_gpc_irq_unmask(struct irq_data *d)
	160	{
	161	/* Sanity check for SPI irq */
	162	if (d->hwirq < 32)
	163	return;
	164
	165	imx_gpc_hwirq_unmask(d->hwirq);
	166	}
	167
	168	static void imx_gpc_irq_mask(struct irq_data *d)
	169	{
9fbbe689	170	/* Sanity check for SPI irq */
e2fd06f6	171	if (d->hwirq < 32)
9fbbe689 SG	172	return;
9fbbe689 SG	173
65bb688a	174	imx_gpc_hwirq_mask(d->hwirq);
9fbbe689 SG	175	}
	176
	177	void __init imx_gpc_init(void)
	178	{
	179	struct device_node *np;
485863b8	180	int i;
9fbbe689 SG	181
	182	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
	183	gpc_base = of_iomap(np, 0);
	184	WARN_ON(!gpc_base);
	185
485863b8 SG	186	/* Initially mask all interrupts */
	187	for (i = 0; i < IMR_NUM; i++)
	188	writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
	189
9fbbe689 SG	190	/* Register GPC as the secondary interrupt controller behind GIC */
	191	gic_arch_extn.irq_mask = imx_gpc_irq_mask;
	192	gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
	193	gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
	194	}
00eb60a8 PZ	195
	196	#ifdef CONFIG_PM_GENERIC_DOMAINS
	197
	198	static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
	199	{
	200	int iso, iso2sw;
	201	u32 val;
	202
	203	/* Read ISO and ISO2SW power down delays */
	204	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
	205	iso = val & 0x3f;
	206	iso2sw = (val >> 8) & 0x3f;
	207
	208	/* Gate off PU domain when GPU/VPU when powered down */
	209	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
	210
	211	/* Request GPC to power down GPU/VPU */
	212	val = readl_relaxed(gpc_base + GPC_CNTR);
	213	val \|= GPU_VPU_PDN_REQ;
	214	writel_relaxed(val, gpc_base + GPC_CNTR);
	215
	216	/* Wait ISO + ISO2SW IPG clock cycles */
	217	ndelay((iso + iso2sw) * 1000 / 66);
	218	}
	219
	220	static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
	221	{
	222	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
	223
	224	_imx6q_pm_pu_power_off(genpd);
	225
	226	if (pu->reg)
	227	regulator_disable(pu->reg);
	228
	229	return 0;
	230	}
	231
	232	static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
	233	{
	234	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
	235	int i, ret, sw, sw2iso;
	236	u32 val;
	237
	238	if (pu->reg)
	239	ret = regulator_enable(pu->reg);
	240	if (pu->reg && ret) {
	241	pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
	242	return ret;
	243	}
	244
	245	/* Enable reset clocks for all devices in the PU domain */
	246	for (i = 0; i < pu->num_clks; i++)
	247	clk_prepare_enable(pu->clk[i]);
	248
	249	/* Gate off PU domain when GPU/VPU when powered down */
	250	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
	251
	252	/* Read ISO and ISO2SW power down delays */
	253	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
	254	sw = val & 0x3f;
	255	sw2iso = (val >> 8) & 0x3f;
	256
	257	/* Request GPC to power up GPU/VPU */
	258	val = readl_relaxed(gpc_base + GPC_CNTR);
259	val \|= GPU_VPU_PUP_REQ;
260	writel_relaxed(val, gpc_base + GPC_CNTR);
261
262	/* Wait ISO + ISO2SW IPG clock cycles */
263	ndelay((sw + sw2iso) * 1000 / 66);
264
265	/* Disable reset clocks for all devices in the PU domain */
266	for (i = 0; i < pu->num_clks; i++)
267	clk_disable_unprepare(pu->clk[i]);
268
269	return 0;
270	}
271
272	static struct generic_pm_domain imx6q_arm_domain = {
273	.name = "ARM",
274	};
275
276	static struct pu_domain imx6q_pu_domain = {
277	.base = {
278	.name = "PU",
279	.power_off = imx6q_pm_pu_power_off,
280	.power_on = imx6q_pm_pu_power_on,
281	.power_off_latency_ns = 25000,
282	.power_on_latency_ns = 2000000,
283	},
284	};
285
286	static struct generic_pm_domain imx6sl_display_domain = {
287	.name = "DISPLAY",
288	};
289
290	static struct generic_pm_domain *imx_gpc_domains[] = {
291	&imx6q_arm_domain,
292	&imx6q_pu_domain.base,
293	&imx6sl_display_domain,
294	};
295
296	static struct genpd_onecell_data imx_gpc_onecell_data = {
297	.domains = imx_gpc_domains,
298	.num_domains = ARRAY_SIZE(imx_gpc_domains),
299	};
300
301	static int imx_gpc_genpd_init(struct device dev, struct regulator pu_reg)
302	{
303	struct clk *clk;
304	bool is_off;
305	int i;
306
307	imx6q_pu_domain.reg = pu_reg;
308
309	for (i = 0; ; i++) {
310	clk = of_clk_get(dev->of_node, i);
311	if (IS_ERR(clk))
312	break;
313	if (i >= GPC_CLK_MAX) {
314	dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
315	goto clk_err;
316	}
317	imx6q_pu_domain.clk[i] = clk;
318	}
319	imx6q_pu_domain.num_clks = i;
320
321	is_off = IS_ENABLED(CONFIG_PM);
322	if (is_off) {
323	_imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
324	} else {
325	/*
326	* Enable power if compiled without CONFIG_PM in case the
327	* bootloader disabled it.
328	*/
329	imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
330	}
331
332	pm_genpd_init(&imx6q_pu_domain.base, NULL, is_off);
333	return of_genpd_add_provider_onecell(dev->of_node,
334	&imx_gpc_onecell_data);
335
336	clk_err:
337	while (i--)
338	clk_put(imx6q_pu_domain.clk[i]);
339	return -EINVAL;
340	}
341
342	#else
343	static inline int imx_gpc_genpd_init(struct device dev, struct regulator reg)
344	{
345	return 0;
346	}
347	#endif /* CONFIG_PM_GENERIC_DOMAINS */
348
349	static int imx_gpc_probe(struct platform_device *pdev)
350	{
351	struct regulator *pu_reg;
352	int ret;
353
354	pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
355	if (PTR_ERR(pu_reg) == -ENODEV)
356	pu_reg = NULL;
357	if (IS_ERR(pu_reg)) {
358	ret = PTR_ERR(pu_reg);
359	dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
360	return ret;
361	}
362
363	return imx_gpc_genpd_init(&pdev->dev, pu_reg);
364	}
365
366	static const struct of_device_id imx_gpc_dt_ids[] = {
367	{ .compatible = "fsl,imx6q-gpc" },
368	{ .compatible = "fsl,imx6sl-gpc" },
369	{ }
370	};
371
372	static struct platform_driver imx_gpc_driver = {
373	.driver = {
374	.name = "imx-gpc",
375	.owner = THIS_MODULE,
376	.of_match_table = imx_gpc_dt_ids,
377	},
378	.probe = imx_gpc_probe,
379	};
380
381	static int __init imx_pgc_init(void)
382	{
383	return platform_driver_register(&imx_gpc_driver);
384	}
385	subsys_initcall(imx_pgc_init);