[linux-block.git] / arch / arm / mach-imx / gpc.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
#include "hardware.h"

#define GPC_CNTR		0x000
#define GPC_IMR1		0x008
#define GPC_PGC_GPU_PDN		0x260
#define GPC_PGC_GPU_PUPSCR	0x264
#define GPC_PGC_GPU_PDNSCR	0x268
#define GPC_PGC_CPU_PDN		0x2a0
#define GPC_PGC_CPU_PUPSCR	0x2a4
#define GPC_PGC_CPU_PDNSCR	0x2a8
#define GPC_PGC_SW2ISO_SHIFT	0x8
#define GPC_PGC_SW_SHIFT	0x0

#define IMR_NUM			4
#define GPC_MAX_IRQS		(IMR_NUM * 32)

#define GPU_VPU_PUP_REQ		BIT(1)
#define GPU_VPU_PDN_REQ		BIT(0)

#define GPC_CLK_MAX		6

struct pu_domain {
	struct generic_pm_domain base;
	struct regulator *reg;
	struct clk *clk[GPC_CLK_MAX];
	int num_clks;
};

static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];

void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
{
	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
}

void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
{
	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
}

void imx_gpc_set_arm_power_in_lpm(bool power_off)
{
	writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
}

void imx_gpc_pre_suspend(bool arm_power_off)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	/* Tell GPC to power off ARM core when suspend */
	if (arm_power_off)
		imx_gpc_set_arm_power_in_lpm(arm_power_off);

	for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
	}
}

void imx_gpc_post_resume(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	/* Keep ARM core powered on for other low-power modes */
	imx_gpc_set_arm_power_in_lpm(false);

	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}

static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
	unsigned int idx = d->hwirq / 32;
	u32 mask;

	mask = 1 << d->hwirq % 32;
	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
				  gpc_wake_irqs[idx] & ~mask;

	/*
	 * Do *not* call into the parent, as the GIC doesn't have any
	 * wake-up facility...
	 */
	return 0;
}

void imx_gpc_mask_all(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~0, reg_imr1 + i * 4);
	}

}

void imx_gpc_restore_all(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}

void imx_gpc_hwirq_unmask(unsigned int hwirq)
{
	void __iomem *reg;
	u32 val;

	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
	val = readl_relaxed(reg);
	val &= ~(1 << hwirq % 32);
	writel_relaxed(val, reg);
}

void imx_gpc_hwirq_mask(unsigned int hwirq)
{
	void __iomem *reg;
	u32 val;

	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
	val = readl_relaxed(reg);
	val |= 1 << (hwirq % 32);
	writel_relaxed(val, reg);
}

static void imx_gpc_irq_unmask(struct irq_data *d)
{
	imx_gpc_hwirq_unmask(d->hwirq);
	irq_chip_unmask_parent(d);
}

static void imx_gpc_irq_mask(struct irq_data *d)
{
	imx_gpc_hwirq_mask(d->hwirq);
	irq_chip_mask_parent(d);
}

static struct irq_chip imx_gpc_chip = {
	.name			= "GPC",
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_mask		= imx_gpc_irq_mask,
	.irq_unmask		= imx_gpc_irq_unmask,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_set_wake		= imx_gpc_irq_set_wake,
#ifdef CONFIG_SMP
	.irq_set_affinity	= irq_chip_set_affinity_parent,
#endif
};

static int imx_gpc_domain_translate(struct irq_domain *d,
				    struct irq_fwspec *fwspec,
				    unsigned long *hwirq,
				    unsigned int *type)
{
	if (is_of_node(fwspec->fwnode)) {
		if (fwspec->param_count != 3)
			return -EINVAL;

		/* No PPI should point to this domain */
		if (fwspec->param[0] != 0)
			return -EINVAL;

		*hwirq = fwspec->param[1];
		*type = fwspec->param[2];
		return 0;
	}

	return -EINVAL;
}

static int imx_gpc_domain_alloc(struct irq_domain *domain,
				  unsigned int irq,
				  unsigned int nr_irqs, void *data)
{
	struct irq_fwspec *fwspec = data;
	struct irq_fwspec parent_fwspec;
	irq_hw_number_t hwirq;
	int i;

	if (fwspec->param_count != 3)
		return -EINVAL;	/* Not GIC compliant */
	if (fwspec->param[0] != 0)
		return -EINVAL;	/* No PPI should point to this domain */

	hwirq = fwspec->param[1];
	if (hwirq >= GPC_MAX_IRQS)
		return -EINVAL;	/* Can't deal with this */

	for (i = 0; i < nr_irqs; i++)
		irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
					      &imx_gpc_chip, NULL);

	parent_fwspec = *fwspec;
	parent_fwspec.fwnode = domain->parent->fwnode;
	return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
					    &parent_fwspec);
}

static const struct irq_domain_ops imx_gpc_domain_ops = {
	.translate	= imx_gpc_domain_translate,
	.alloc		= imx_gpc_domain_alloc,
	.free		= irq_domain_free_irqs_common,
};

static int __init imx_gpc_init(struct device_node *node,
			       struct device_node *parent)
{
	struct irq_domain *parent_domain, *domain;
	int i;

	if (!parent) {
		pr_err("%s: no parent, giving up\n", node->full_name);
		return -ENODEV;
	}

	parent_domain = irq_find_host(parent);
	if (!parent_domain) {
		pr_err("%s: unable to obtain parent domain\n", node->full_name);
		return -ENXIO;
	}

	gpc_base = of_iomap(node, 0);
	if (WARN_ON(!gpc_base))
	        return -ENOMEM;

	domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
					  node, &imx_gpc_domain_ops,
					  NULL);
	if (!domain) {
		iounmap(gpc_base);
		return -ENOMEM;
	}

	/* Initially mask all interrupts */
	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);

	return 0;
}

/*
 * We cannot use the IRQCHIP_DECLARE macro that lives in
 * drivers/irqchip, so we're forced to roll our own. Not very nice.
 */
OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);

void __init imx_gpc_check_dt(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
	if (WARN_ON(!np))
		return;

	if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
		pr_warn("Outdated DT detected, suspend/resume will NOT work\n");

		/* map GPC, so that at least CPUidle and WARs keep working */
		gpc_base = of_iomap(np, 0);
	}
}

static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
	int iso, iso2sw;
	u32 val;

	/* Read ISO and ISO2SW power down delays */
	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
	iso = val & 0x3f;
	iso2sw = (val >> 8) & 0x3f;

	/* Gate off PU domain when GPU/VPU when powered down */
	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);

	/* Request GPC to power down GPU/VPU */
	val = readl_relaxed(gpc_base + GPC_CNTR);
	val |= GPU_VPU_PDN_REQ;
	writel_relaxed(val, gpc_base + GPC_CNTR);

	/* Wait ISO + ISO2SW IPG clock cycles */
	ndelay((iso + iso2sw) * 1000 / 66);
}

static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);

	_imx6q_pm_pu_power_off(genpd);

	if (pu->reg)
		regulator_disable(pu->reg);

	return 0;
}

static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
{
	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
	int i, ret, sw, sw2iso;
	u32 val;

	if (pu->reg)
		ret = regulator_enable(pu->reg);
	if (pu->reg && ret) {
		pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
		return ret;
	}

	/* Enable reset clocks for all devices in the PU domain */
	for (i = 0; i < pu->num_clks; i++)
		clk_prepare_enable(pu->clk[i]);

	/* Gate off PU domain when GPU/VPU when powered down */
	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);

	/* Read ISO and ISO2SW power down delays */
	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
	sw = val & 0x3f;
	sw2iso = (val >> 8) & 0x3f;

	/* Request GPC to power up GPU/VPU */
	val = readl_relaxed(gpc_base + GPC_CNTR);
	val |= GPU_VPU_PUP_REQ;
	writel_relaxed(val, gpc_base + GPC_CNTR);

	/* Wait ISO + ISO2SW IPG clock cycles */
	ndelay((sw + sw2iso) * 1000 / 66);

	/* Disable reset clocks for all devices in the PU domain */
	for (i = 0; i < pu->num_clks; i++)
		clk_disable_unprepare(pu->clk[i]);

	return 0;
}

static struct generic_pm_domain imx6q_arm_domain = {
	.name = "ARM",
};

static struct pu_domain imx6q_pu_domain = {
	.base = {
		.name = "PU",
		.power_off = imx6q_pm_pu_power_off,
		.power_on = imx6q_pm_pu_power_on,
		.power_off_latency_ns = 25000,
		.power_on_latency_ns = 2000000,
	},
};

static struct generic_pm_domain imx6sl_display_domain = {
	.name = "DISPLAY",
};

static struct generic_pm_domain *imx_gpc_domains[] = {
	&imx6q_arm_domain,
	&imx6q_pu_domain.base,
	&imx6sl_display_domain,
};

static struct genpd_onecell_data imx_gpc_onecell_data = {
	.domains = imx_gpc_domains,
	.num_domains = ARRAY_SIZE(imx_gpc_domains),
};

static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
{
	struct clk *clk;
	int i;

	imx6q_pu_domain.reg = pu_reg;

	for (i = 0; ; i++) {
		clk = of_clk_get(dev->of_node, i);
		if (IS_ERR(clk))
			break;
		if (i >= GPC_CLK_MAX) {
			dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
			goto clk_err;
		}
		imx6q_pu_domain.clk[i] = clk;
	}
	imx6q_pu_domain.num_clks = i;

	/* Enable power always in case bootloader disabled it. */
	imx6q_pm_pu_power_on(&imx6q_pu_domain.base);

	if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
		return 0;

	pm_genpd_init(&imx6q_pu_domain.base, NULL, false);
	return of_genpd_add_provider_onecell(dev->of_node,
					     &imx_gpc_onecell_data);

clk_err:
	while (i--)
		clk_put(imx6q_pu_domain.clk[i]);
	return -EINVAL;
}

static int imx_gpc_probe(struct platform_device *pdev)
{
	struct regulator *pu_reg;
	int ret;

	/* bail out if DT too old and doesn't provide the necessary info */
	if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
		return 0;

	pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
	if (PTR_ERR(pu_reg) == -ENODEV)
		pu_reg = NULL;
	if (IS_ERR(pu_reg)) {
		ret = PTR_ERR(pu_reg);
		dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
		return ret;
	}

	return imx_gpc_genpd_init(&pdev->dev, pu_reg);
}

static const struct of_device_id imx_gpc_dt_ids[] = {
	{ .compatible = "fsl,imx6q-gpc" },
	{ .compatible = "fsl,imx6sl-gpc" },
	{ }
};

static struct platform_driver imx_gpc_driver = {
	.driver = {
		.name = "imx-gpc",
		.of_match_table = imx_gpc_dt_ids,
	},
	.probe = imx_gpc_probe,
};

static int __init imx_pgc_init(void)
{
	return platform_driver_register(&imx_gpc_driver);
}
subsys_initcall(imx_pgc_init);
Commit	Line	Data
9fbbe689	1	/*
263475d4	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
9fbbe689 SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
00eb60a8 PZ	13	#include <linux/clk.h>
00eb60a8 PZ	14	#include <linux/delay.h>
9fbbe689 SG	15	#include <linux/io.h>
	16	#include <linux/irq.h>
	17	#include <linux/of.h>
	18	#include <linux/of_address.h>
	19	#include <linux/of_irq.h>
00eb60a8 PZ	20	#include <linux/platform_device.h>
	21	#include <linux/pm_domain.h>
	22	#include <linux/regulator/consumer.h>
520f7bd7	23	#include <linux/irqchip/arm-gic.h>
9a67a6fd	24	#include "common.h"
00eb60a8	25	#include "hardware.h"
9fbbe689	26
00eb60a8	27	#define GPC_CNTR 0x000
9fbbe689	28	#define GPC_IMR1 0x008
00eb60a8 PZ	29	#define GPC_PGC_GPU_PDN 0x260
	30	#define GPC_PGC_GPU_PUPSCR 0x264
	31	#define GPC_PGC_GPU_PDNSCR 0x268
9fbbe689	32	#define GPC_PGC_CPU_PDN 0x2a0
05136f08 AH	33	#define GPC_PGC_CPU_PUPSCR 0x2a4
	34	#define GPC_PGC_CPU_PDNSCR 0x2a8
	35	#define GPC_PGC_SW2ISO_SHIFT 0x8
	36	#define GPC_PGC_SW_SHIFT 0x0
9fbbe689 SG	37
9fbbe689 SG	38	#define IMR_NUM 4
b923ff6a	39	#define GPC_MAX_IRQS (IMR_NUM * 32)
9fbbe689	40
00eb60a8 PZ	41	#define GPU_VPU_PUP_REQ BIT(1)
	42	#define GPU_VPU_PDN_REQ BIT(0)
	43
	44	#define GPC_CLK_MAX 6
	45
	46	struct pu_domain {
	47	struct generic_pm_domain base;
	48	struct regulator *reg;
	49	struct clk *clk[GPC_CLK_MAX];
	50	int num_clks;
	51	};
	52
9fbbe689 SG	53	static void __iomem *gpc_base;
	54	static u32 gpc_wake_irqs[IMR_NUM];
	55	static u32 gpc_saved_imrs[IMR_NUM];
	56
05136f08 AH	57	void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
	58	{
	59	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) \|
	60	(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
	61	}
	62
	63	void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
	64	{
	65	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) \|
	66	(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
	67	}
	68
	69	void imx_gpc_set_arm_power_in_lpm(bool power_off)
	70	{
	71	writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
	72	}
	73
80c0ecdc	74	void imx_gpc_pre_suspend(bool arm_power_off)
9fbbe689 SG	75	{
	76	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	77	int i;
	78
	79	/* Tell GPC to power off ARM core when suspend */
80c0ecdc	80	if (arm_power_off)
05136f08	81	imx_gpc_set_arm_power_in_lpm(arm_power_off);
9fbbe689 SG	82
	83	for (i = 0; i < IMR_NUM; i++) {
	84	gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
	85	writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
	86	}
	87	}
	88
	89	void imx_gpc_post_resume(void)
	90	{
	91	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	92	int i;
	93
	94	/* Keep ARM core powered on for other low-power modes */
05136f08	95	imx_gpc_set_arm_power_in_lpm(false);
9fbbe689 SG	96
	97	for (i = 0; i < IMR_NUM; i++)
	98	writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
	99	}
	100
	101	static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
	102	{
b923ff6a	103	unsigned int idx = d->hwirq / 32;
9fbbe689 SG	104	u32 mask;
9fbbe689 SG	105
e2fd06f6	106	mask = 1 << d->hwirq % 32;
9fbbe689 SG	107	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] \| mask :
	108	gpc_wake_irqs[idx] & ~mask;
	109
b923ff6a MZ	110	/*
	111	* Do not call into the parent, as the GIC doesn't have any
	112	* wake-up facility...
	113	*/
9fbbe689 SG	114	return 0;
	115	}
	116
263475d4 AH	117	void imx_gpc_mask_all(void)
	118	{
	119	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	120	int i;
	121
	122	for (i = 0; i < IMR_NUM; i++) {
	123	gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
	124	writel_relaxed(~0, reg_imr1 + i * 4);
	125	}
	126
	127	}
	128
	129	void imx_gpc_restore_all(void)
	130	{
	131	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	132	int i;
	133
	134	for (i = 0; i < IMR_NUM; i++)
	135	writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
	136	}
	137
65bb688a	138	void imx_gpc_hwirq_unmask(unsigned int hwirq)
9fbbe689 SG	139	{
	140	void __iomem *reg;
	141	u32 val;
	142
b923ff6a	143	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
9fbbe689	144	val = readl_relaxed(reg);
65bb688a	145	val &= ~(1 << hwirq % 32);
9fbbe689 SG	146	writel_relaxed(val, reg);
	147	}
	148
65bb688a	149	void imx_gpc_hwirq_mask(unsigned int hwirq)
9fbbe689 SG	150	{
	151	void __iomem *reg;
	152	u32 val;
	153
b923ff6a	154	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
65bb688a MZ	155	val = readl_relaxed(reg);
	156	val \|= 1 << (hwirq % 32);
	157	writel_relaxed(val, reg);
	158	}
	159
	160	static void imx_gpc_irq_unmask(struct irq_data *d)
	161	{
65bb688a	162	imx_gpc_hwirq_unmask(d->hwirq);
b923ff6a	163	irq_chip_unmask_parent(d);
65bb688a MZ	164	}
	165
	166	static void imx_gpc_irq_mask(struct irq_data *d)
	167	{
65bb688a	168	imx_gpc_hwirq_mask(d->hwirq);
b923ff6a	169	irq_chip_mask_parent(d);
9fbbe689 SG	170	}
9fbbe689 SG	171
b923ff6a	172	static struct irq_chip imx_gpc_chip = {
e33b6752 MZ	173	.name = "GPC",
	174	.irq_eoi = irq_chip_eoi_parent,
	175	.irq_mask = imx_gpc_irq_mask,
	176	.irq_unmask = imx_gpc_irq_unmask,
	177	.irq_retrigger = irq_chip_retrigger_hierarchy,
	178	.irq_set_wake = imx_gpc_irq_set_wake,
	179	#ifdef CONFIG_SMP
	180	.irq_set_affinity = irq_chip_set_affinity_parent,
	181	#endif
b923ff6a MZ	182	};
b923ff6a MZ	183
f833f57f MZ	184	static int imx_gpc_domain_translate(struct irq_domain *d,
	185	struct irq_fwspec *fwspec,
	186	unsigned long *hwirq,
	187	unsigned int *type)
9fbbe689	188	{
f833f57f MZ	189	if (is_of_node(fwspec->fwnode)) {
	190	if (fwspec->param_count != 3)
	191	return -EINVAL;
b923ff6a	192
f833f57f MZ	193	/* No PPI should point to this domain */
	194	if (fwspec->param[0] != 0)
	195	return -EINVAL;
	196
	197	*hwirq = fwspec->param[1];
	198	*type = fwspec->param[2];
	199	return 0;
	200	}
	201
	202	return -EINVAL;
b923ff6a MZ	203	}
	204
	205	static int imx_gpc_domain_alloc(struct irq_domain *domain,
	206	unsigned int irq,
	207	unsigned int nr_irqs, void *data)
	208	{
f833f57f MZ	209	struct irq_fwspec *fwspec = data;
f833f57f MZ	210	struct irq_fwspec parent_fwspec;
b923ff6a	211	irq_hw_number_t hwirq;
485863b8	212	int i;
9fbbe689	213
f833f57f	214	if (fwspec->param_count != 3)
b923ff6a	215	return -EINVAL; /* Not GIC compliant */
f833f57f	216	if (fwspec->param[0] != 0)
b923ff6a MZ	217	return -EINVAL; /* No PPI should point to this domain */
b923ff6a MZ	218
f833f57f	219	hwirq = fwspec->param[1];
b923ff6a MZ	220	if (hwirq >= GPC_MAX_IRQS)
	221	return -EINVAL; /* Can't deal with this */
	222
	223	for (i = 0; i < nr_irqs; i++)
	224	irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
	225	&imx_gpc_chip, NULL);
	226
f833f57f MZ	227	parent_fwspec = *fwspec;
	228	parent_fwspec.fwnode = domain->parent->fwnode;
	229	return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
	230	&parent_fwspec);
b923ff6a MZ	231	}
b923ff6a MZ	232
9b589a83	233	static const struct irq_domain_ops imx_gpc_domain_ops = {
f833f57f MZ	234	.translate = imx_gpc_domain_translate,
	235	.alloc = imx_gpc_domain_alloc,
	236	.free = irq_domain_free_irqs_common,
b923ff6a MZ	237	};
	238
	239	static int __init imx_gpc_init(struct device_node *node,
	240	struct device_node *parent)
	241	{
	242	struct irq_domain parent_domain, domain;
	243	int i;
	244
	245	if (!parent) {
	246	pr_err("%s: no parent, giving up\n", node->full_name);
	247	return -ENODEV;
	248	}
	249
	250	parent_domain = irq_find_host(parent);
	251	if (!parent_domain) {
	252	pr_err("%s: unable to obtain parent domain\n", node->full_name);
	253	return -ENXIO;
	254	}
	255
	256	gpc_base = of_iomap(node, 0);
	257	if (WARN_ON(!gpc_base))
	258	return -ENOMEM;
	259
	260	domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
	261	node, &imx_gpc_domain_ops,
	262	NULL);
	263	if (!domain) {
	264	iounmap(gpc_base);
	265	return -ENOMEM;
	266	}
9fbbe689	267
485863b8 SG	268	/* Initially mask all interrupts */
	269	for (i = 0; i < IMR_NUM; i++)
	270	writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
	271
b923ff6a	272	return 0;
9fbbe689	273	}
00eb60a8	274
b923ff6a MZ	275	/*
	276	* We cannot use the IRQCHIP_DECLARE macro that lives in
	277	* drivers/irqchip, so we're forced to roll our own. Not very nice.
	278	*/
	279	OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
	280
14517564 MZ	281	void __init imx_gpc_check_dt(void)
	282	{
	283	struct device_node *np;
	284
	285	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
634a6037 LS	286	if (WARN_ON(!np))
	287	return;
	288
	289	if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
	290	pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
	291
	292	/* map GPC, so that at least CPUidle and WARs keep working */
	293	gpc_base = of_iomap(np, 0);
	294	}
14517564 MZ	295	}
14517564 MZ	296
00eb60a8 PZ	297	static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
	298	{
	299	int iso, iso2sw;
	300	u32 val;
	301
	302	/* Read ISO and ISO2SW power down delays */
	303	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
	304	iso = val & 0x3f;
	305	iso2sw = (val >> 8) & 0x3f;
	306
	307	/* Gate off PU domain when GPU/VPU when powered down */
	308	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
	309
	310	/* Request GPC to power down GPU/VPU */
	311	val = readl_relaxed(gpc_base + GPC_CNTR);
	312	val \|= GPU_VPU_PDN_REQ;
	313	writel_relaxed(val, gpc_base + GPC_CNTR);
	314
	315	/* Wait ISO + ISO2SW IPG clock cycles */
	316	ndelay((iso + iso2sw) * 1000 / 66);
	317	}
	318
	319	static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
	320	{
	321	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
	322
	323	_imx6q_pm_pu_power_off(genpd);
	324
	325	if (pu->reg)
	326	regulator_disable(pu->reg);
	327
	328	return 0;
	329	}
	330
	331	static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
	332	{
	333	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
	334	int i, ret, sw, sw2iso;
	335	u32 val;
	336
	337	if (pu->reg)
	338	ret = regulator_enable(pu->reg);
	339	if (pu->reg && ret) {
	340	pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
	341	return ret;
	342	}
	343
	344	/* Enable reset clocks for all devices in the PU domain */
	345	for (i = 0; i < pu->num_clks; i++)
	346	clk_prepare_enable(pu->clk[i]);
	347
	348	/* Gate off PU domain when GPU/VPU when powered down */
	349	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
	350
	351	/* Read ISO and ISO2SW power down delays */
	352	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
	353	sw = val & 0x3f;
	354	sw2iso = (val >> 8) & 0x3f;
	355
	356	/* Request GPC to power up GPU/VPU */
	357	val = readl_relaxed(gpc_base + GPC_CNTR);
	358	val \|= GPU_VPU_PUP_REQ;
	359	writel_relaxed(val, gpc_base + GPC_CNTR);
	360
361	/* Wait ISO + ISO2SW IPG clock cycles */
362	ndelay((sw + sw2iso) * 1000 / 66);
363
364	/* Disable reset clocks for all devices in the PU domain */
365	for (i = 0; i < pu->num_clks; i++)
366	clk_disable_unprepare(pu->clk[i]);
367
368	return 0;
369	}
370
371	static struct generic_pm_domain imx6q_arm_domain = {
372	.name = "ARM",
373	};
374
375	static struct pu_domain imx6q_pu_domain = {
376	.base = {
377	.name = "PU",
378	.power_off = imx6q_pm_pu_power_off,
379	.power_on = imx6q_pm_pu_power_on,
380	.power_off_latency_ns = 25000,
381	.power_on_latency_ns = 2000000,
382	},
383	};
384
385	static struct generic_pm_domain imx6sl_display_domain = {
386	.name = "DISPLAY",
387	};
388
389	static struct generic_pm_domain *imx_gpc_domains[] = {
390	&imx6q_arm_domain,
391	&imx6q_pu_domain.base,
392	&imx6sl_display_domain,
393	};
394
395	static struct genpd_onecell_data imx_gpc_onecell_data = {
396	.domains = imx_gpc_domains,
397	.num_domains = ARRAY_SIZE(imx_gpc_domains),
398	};
399
400	static int imx_gpc_genpd_init(struct device dev, struct regulator pu_reg)
401	{
402	struct clk *clk;
00eb60a8 PZ	403	int i;
	404
	405	imx6q_pu_domain.reg = pu_reg;
	406
	407	for (i = 0; ; i++) {
	408	clk = of_clk_get(dev->of_node, i);
	409	if (IS_ERR(clk))
	410	break;
	411	if (i >= GPC_CLK_MAX) {
	412	dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
	413	goto clk_err;
	414	}
	415	imx6q_pu_domain.clk[i] = clk;
	416	}
	417	imx6q_pu_domain.num_clks = i;
	418
d438462c LS	419	/* Enable power always in case bootloader disabled it. */
	420	imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
	421
	422	if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
	423	return 0;
00eb60a8	424
d438462c	425	pm_genpd_init(&imx6q_pu_domain.base, NULL, false);
00eb60a8 PZ	426	return of_genpd_add_provider_onecell(dev->of_node,
	427	&imx_gpc_onecell_data);
	428
	429	clk_err:
	430	while (i--)
	431	clk_put(imx6q_pu_domain.clk[i]);
	432	return -EINVAL;
	433	}
	434
00eb60a8 PZ	435	static int imx_gpc_probe(struct platform_device *pdev)
	436	{
	437	struct regulator *pu_reg;
	438	int ret;
	439
b17c70cd LS	440	/* bail out if DT too old and doesn't provide the necessary info */
	441	if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
	442	return 0;
	443
00eb60a8 PZ	444	pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
	445	if (PTR_ERR(pu_reg) == -ENODEV)
	446	pu_reg = NULL;
	447	if (IS_ERR(pu_reg)) {
	448	ret = PTR_ERR(pu_reg);
	449	dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
	450	return ret;
	451	}
	452
	453	return imx_gpc_genpd_init(&pdev->dev, pu_reg);
	454	}
	455
	456	static const struct of_device_id imx_gpc_dt_ids[] = {
	457	{ .compatible = "fsl,imx6q-gpc" },
	458	{ .compatible = "fsl,imx6sl-gpc" },
	459	{ }
	460	};
	461
	462	static struct platform_driver imx_gpc_driver = {
	463	.driver = {
	464	.name = "imx-gpc",
00eb60a8 PZ	465	.of_match_table = imx_gpc_dt_ids,
	466	},
	467	.probe = imx_gpc_probe,
	468	};
	469
	470	static int __init imx_pgc_init(void)
	471	{
	472	return platform_driver_register(&imx_gpc_driver);
	473	}
	474	subsys_initcall(imx_pgc_init);