[linux-2.6-block.git] / arch / arm / mach-imx / gpc.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"

#define GPC_IMR1		0x008
#define GPC_PGC_CPU_PDN		0x2a0

#define IMR_NUM			4

static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];

void imx_gpc_pre_suspend(bool arm_power_off)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	/* Tell GPC to power off ARM core when suspend */
	if (arm_power_off)
		writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);

	for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
	}
}

void imx_gpc_post_resume(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	/* Keep ARM core powered on for other low-power modes */
	writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);

	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}

static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
	unsigned int idx = d->hwirq / 32 - 1;
	u32 mask;

	/* Sanity check for SPI irq */
	if (d->hwirq < 32)
		return -EINVAL;

	mask = 1 << d->hwirq % 32;
	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
				  gpc_wake_irqs[idx] & ~mask;

	return 0;
}

void imx_gpc_mask_all(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~0, reg_imr1 + i * 4);
	}

}

void imx_gpc_restore_all(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}

void imx_gpc_hwirq_unmask(unsigned int hwirq)
{
	void __iomem *reg;
	u32 val;

	reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
	val = readl_relaxed(reg);
	val &= ~(1 << hwirq % 32);
	writel_relaxed(val, reg);
}

void imx_gpc_hwirq_mask(unsigned int hwirq)
{
	void __iomem *reg;
	u32 val;

	reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
	val = readl_relaxed(reg);
	val |= 1 << (hwirq % 32);
	writel_relaxed(val, reg);
}

static void imx_gpc_irq_unmask(struct irq_data *d)
{
	/* Sanity check for SPI irq */
	if (d->hwirq < 32)
		return;

	imx_gpc_hwirq_unmask(d->hwirq);
}

static void imx_gpc_irq_mask(struct irq_data *d)
{
	/* Sanity check for SPI irq */
	if (d->hwirq < 32)
		return;

	imx_gpc_hwirq_mask(d->hwirq);
}

void __init imx_gpc_init(void)
{
	struct device_node *np;
	int i;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
	gpc_base = of_iomap(np, 0);
	WARN_ON(!gpc_base);

	/* Initially mask all interrupts */
	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);

	/* Register GPC as the secondary interrupt controller behind GIC */
	gic_arch_extn.irq_mask = imx_gpc_irq_mask;
	gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
	gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
}
Commit	Line	Data
9fbbe689	1	/*
263475d4	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
9fbbe689 SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	#include <linux/io.h>
	14	#include <linux/irq.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
520f7bd7	18	#include <linux/irqchip/arm-gic.h>
9a67a6fd	19	#include "common.h"
9fbbe689 SG	20
	21	#define GPC_IMR1 0x008
	22	#define GPC_PGC_CPU_PDN 0x2a0
	23
	24	#define IMR_NUM 4
	25
	26	static void __iomem *gpc_base;
	27	static u32 gpc_wake_irqs[IMR_NUM];
	28	static u32 gpc_saved_imrs[IMR_NUM];
	29
80c0ecdc	30	void imx_gpc_pre_suspend(bool arm_power_off)
9fbbe689 SG	31	{
	32	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	33	int i;
	34
	35	/* Tell GPC to power off ARM core when suspend */
80c0ecdc AH	36	if (arm_power_off)
80c0ecdc AH	37	writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
9fbbe689 SG	38
	39	for (i = 0; i < IMR_NUM; i++) {
	40	gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
	41	writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
	42	}
	43	}
	44
	45	void imx_gpc_post_resume(void)
	46	{
	47	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	48	int i;
	49
	50	/* Keep ARM core powered on for other low-power modes */
	51	writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
	52
	53	for (i = 0; i < IMR_NUM; i++)
	54	writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
	55	}
	56
	57	static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
	58	{
e2fd06f6	59	unsigned int idx = d->hwirq / 32 - 1;
9fbbe689 SG	60	u32 mask;
	61
	62	/* Sanity check for SPI irq */
e2fd06f6	63	if (d->hwirq < 32)
9fbbe689 SG	64	return -EINVAL;
9fbbe689 SG	65
e2fd06f6	66	mask = 1 << d->hwirq % 32;
9fbbe689 SG	67	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] \| mask :
	68	gpc_wake_irqs[idx] & ~mask;
	69
	70	return 0;
	71	}
	72
263475d4 AH	73	void imx_gpc_mask_all(void)
	74	{
	75	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	76	int i;
	77
	78	for (i = 0; i < IMR_NUM; i++) {
	79	gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
	80	writel_relaxed(~0, reg_imr1 + i * 4);
	81	}
	82
	83	}
	84
	85	void imx_gpc_restore_all(void)
	86	{
	87	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	88	int i;
	89
	90	for (i = 0; i < IMR_NUM; i++)
	91	writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
	92	}
	93
65bb688a	94	void imx_gpc_hwirq_unmask(unsigned int hwirq)
9fbbe689 SG	95	{
	96	void __iomem *reg;
	97	u32 val;
	98
65bb688a	99	reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
9fbbe689	100	val = readl_relaxed(reg);
65bb688a	101	val &= ~(1 << hwirq % 32);
9fbbe689 SG	102	writel_relaxed(val, reg);
	103	}
	104
65bb688a	105	void imx_gpc_hwirq_mask(unsigned int hwirq)
9fbbe689 SG	106	{
	107	void __iomem *reg;
	108	u32 val;
	109
65bb688a MZ	110	reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
	111	val = readl_relaxed(reg);
	112	val \|= 1 << (hwirq % 32);
	113	writel_relaxed(val, reg);
	114	}
	115
	116	static void imx_gpc_irq_unmask(struct irq_data *d)
	117	{
	118	/* Sanity check for SPI irq */
	119	if (d->hwirq < 32)
	120	return;
	121
	122	imx_gpc_hwirq_unmask(d->hwirq);
	123	}
	124
	125	static void imx_gpc_irq_mask(struct irq_data *d)
	126	{
9fbbe689	127	/* Sanity check for SPI irq */
e2fd06f6	128	if (d->hwirq < 32)
9fbbe689 SG	129	return;
9fbbe689 SG	130
65bb688a	131	imx_gpc_hwirq_mask(d->hwirq);
9fbbe689 SG	132	}
	133
	134	void __init imx_gpc_init(void)
	135	{
	136	struct device_node *np;
485863b8	137	int i;
9fbbe689 SG	138
	139	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
	140	gpc_base = of_iomap(np, 0);
	141	WARN_ON(!gpc_base);
	142
485863b8 SG	143	/* Initially mask all interrupts */
	144	for (i = 0; i < IMR_NUM; i++)
	145	writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
	146
9fbbe689 SG	147	/* Register GPC as the secondary interrupt controller behind GIC */
	148	gic_arch_extn.irq_mask = imx_gpc_irq_mask;
	149	gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
	150	gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
	151	}