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3c8cd0cc PP |
1 | /* |
2 | * cpu.c: clock scaling for the iMX | |
3 | * | |
4 | * Copyright (C) 2000 2001, The Delft University of Technology | |
5 | * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> | |
6 | * Copyright (C) 2006 Inky Lung <ilung@cwlinux.com> | |
7 | * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> | |
8 | * | |
9 | * Based on SA1100 version written by: | |
10 | * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version | |
11 | * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl): | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
26 | * | |
27 | */ | |
28 | ||
29 | /*#define DEBUG*/ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/types.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <asm/system.h> | |
36 | ||
37 | #include <asm/hardware.h> | |
38 | ||
39 | #include "generic.h" | |
40 | ||
41 | #ifndef __val2mfld | |
42 | #define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask)) | |
43 | #endif | |
44 | #ifndef __mfld2val | |
45 | #define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1))) | |
46 | #endif | |
47 | ||
48 | #define CR_920T_CLOCK_MODE 0xC0000000 | |
49 | #define CR_920T_FASTBUS_MODE 0x00000000 | |
50 | #define CR_920T_ASYNC_MODE 0xC0000000 | |
51 | ||
52 | static u32 mpctl0_at_boot; | |
83b84c4e | 53 | static u32 bclk_div_at_boot; |
3c8cd0cc PP |
54 | |
55 | static void imx_set_async_mode(void) | |
56 | { | |
57 | adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE); | |
58 | } | |
59 | ||
60 | static void imx_set_fastbus_mode(void) | |
61 | { | |
62 | adjust_cr(CR_920T_CLOCK_MODE, CR_920T_FASTBUS_MODE); | |
63 | } | |
64 | ||
65 | static void imx_set_mpctl0(u32 mpctl0) | |
66 | { | |
67 | unsigned long flags; | |
68 | ||
69 | if (mpctl0 == 0) { | |
70 | local_irq_save(flags); | |
71 | CSCR &= ~CSCR_MPEN; | |
72 | local_irq_restore(flags); | |
73 | return; | |
74 | } | |
75 | ||
76 | local_irq_save(flags); | |
77 | MPCTL0 = mpctl0; | |
78 | CSCR |= CSCR_MPEN; | |
79 | local_irq_restore(flags); | |
80 | } | |
81 | ||
82 | /** | |
83 | * imx_compute_mpctl - compute new PLL parameters | |
84 | * @new_mpctl: pointer to location assigned by new PLL control register value | |
85 | * @cur_mpctl: current PLL control register parameters | |
b3c6b76f | 86 | * @f_ref: reference source frequency Hz |
3c8cd0cc PP |
87 | * @freq: required frequency in Hz |
88 | * @relation: is one of %CPUFREQ_RELATION_L (supremum) | |
89 | * and %CPUFREQ_RELATION_H (infimum) | |
90 | */ | |
b3c6b76f | 91 | long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, u32 f_ref, unsigned long freq, int relation) |
3c8cd0cc | 92 | { |
3c8cd0cc PP |
93 | u32 mfi; |
94 | u32 mfn; | |
95 | u32 mfd; | |
96 | u32 pd; | |
97 | unsigned long long ll; | |
98 | long l; | |
99 | long quot; | |
100 | ||
101 | /* Fdppl=2*Fref*(MFI+MFN/(MFD+1))/(PD+1) */ | |
102 | /* PD=<0,15>, MFD=<1,1023>, MFI=<5,15> MFN=<0,1022> */ | |
103 | ||
104 | if (cur_mpctl) { | |
105 | mfd = ((cur_mpctl >> 16) & 0x3ff) + 1; | |
106 | pd = ((cur_mpctl >> 26) & 0xf) + 1; | |
107 | } else { | |
108 | pd=2; mfd=313; | |
109 | } | |
110 | ||
111 | /* pd=2; mfd=313; mfi=8; mfn=183; */ | |
112 | /* (MFI+MFN/(MFD)) = Fdppl / (2*Fref) * (PD); */ | |
113 | ||
114 | quot = (f_ref + (1 << 9)) >> 10; | |
115 | l = (freq * pd + quot) / (2 * quot); | |
116 | mfi = l >> 10; | |
117 | mfn = ((l & ((1 << 10) - 1)) * mfd + (1 << 9)) >> 10; | |
118 | ||
119 | mfd -= 1; | |
120 | pd -= 1; | |
121 | ||
122 | *new_mpctl = ((mfi & 0xf) << 10) | (mfn & 0x3ff) | ((mfd & 0x3ff) << 16) | |
123 | | ((pd & 0xf) << 26); | |
124 | ||
125 | ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) ); | |
126 | quot = (pd+1) * (1<<16); | |
127 | ll += quot / 2; | |
128 | do_div(ll, quot); | |
129 | freq = ll; | |
130 | ||
131 | pr_debug(KERN_DEBUG "imx: new PLL parameters pd=%d mfd=%d mfi=%d mfn=%d, freq=%ld\n", | |
132 | pd, mfd, mfi, mfn, freq); | |
133 | ||
134 | return freq; | |
135 | } | |
136 | ||
137 | ||
138 | static int imx_verify_speed(struct cpufreq_policy *policy) | |
139 | { | |
140 | if (policy->cpu != 0) | |
141 | return -EINVAL; | |
142 | ||
143 | cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | static unsigned int imx_get_speed(unsigned int cpu) | |
149 | { | |
150 | unsigned int freq; | |
151 | unsigned int cr; | |
152 | unsigned int cscr; | |
153 | unsigned int bclk_div; | |
154 | ||
155 | if (cpu) | |
156 | return 0; | |
157 | ||
158 | cscr = CSCR; | |
159 | bclk_div = __mfld2val(CSCR_BCLK_DIV, cscr) + 1; | |
160 | cr = get_cr(); | |
161 | ||
162 | if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) { | |
163 | freq = imx_get_system_clk(); | |
164 | freq = (freq + bclk_div/2) / bclk_div; | |
165 | } else { | |
166 | freq = imx_get_mcu_clk(); | |
167 | if (cscr & CSCR_MPU_PRESC) | |
168 | freq /= 2; | |
169 | } | |
170 | ||
171 | freq = (freq + 500) / 1000; | |
172 | ||
173 | return freq; | |
174 | } | |
175 | ||
176 | static int imx_set_target(struct cpufreq_policy *policy, | |
177 | unsigned int target_freq, | |
178 | unsigned int relation) | |
179 | { | |
180 | struct cpufreq_freqs freqs; | |
181 | u32 mpctl0 = 0; | |
182 | u32 cscr; | |
183 | unsigned long flags; | |
184 | long freq; | |
185 | long sysclk; | |
83b84c4e | 186 | unsigned int bclk_div = bclk_div_at_boot; |
3c8cd0cc | 187 | |
5225cd80 PP |
188 | /* |
189 | * Some governors do not respects CPU and policy lower limits | |
190 | * which leads to bad things (division by zero etc), ensure | |
191 | * that such things do not happen. | |
192 | */ | |
193 | if(target_freq < policy->cpuinfo.min_freq) | |
194 | target_freq = policy->cpuinfo.min_freq; | |
195 | ||
196 | if(target_freq < policy->min) | |
197 | target_freq = policy->min; | |
198 | ||
3c8cd0cc PP |
199 | freq = target_freq * 1000; |
200 | ||
201 | pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n", | |
202 | freq, mpctl0_at_boot); | |
203 | ||
204 | sysclk = imx_get_system_clk(); | |
205 | ||
83b84c4e | 206 | if (freq > sysclk / bclk_div_at_boot + 1000000) { |
b3c6b76f | 207 | freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation); |
3c8cd0cc PP |
208 | if (freq < 0) { |
209 | printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq); | |
210 | return -EINVAL; | |
211 | } | |
212 | } else { | |
213 | if(freq + 1000 < sysclk) { | |
214 | if (relation == CPUFREQ_RELATION_L) | |
215 | bclk_div = (sysclk - 1000) / freq; | |
216 | else | |
217 | bclk_div = (sysclk + freq + 1000) / freq; | |
218 | ||
219 | if(bclk_div > 16) | |
220 | bclk_div = 16; | |
83b84c4e PP |
221 | if(bclk_div < bclk_div_at_boot) |
222 | bclk_div = bclk_div_at_boot; | |
3c8cd0cc PP |
223 | } |
224 | freq = (sysclk + bclk_div / 2) / bclk_div; | |
225 | } | |
226 | ||
227 | freqs.old = imx_get_speed(0); | |
228 | freqs.new = (freq + 500) / 1000; | |
229 | freqs.cpu = 0; | |
230 | freqs.flags = 0; | |
231 | ||
232 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
233 | ||
234 | local_irq_save(flags); | |
235 | ||
236 | imx_set_fastbus_mode(); | |
237 | ||
238 | imx_set_mpctl0(mpctl0); | |
239 | ||
240 | cscr = CSCR; | |
241 | cscr &= ~CSCR_BCLK_DIV; | |
242 | cscr |= __val2mfld(CSCR_BCLK_DIV, bclk_div - 1); | |
243 | CSCR = cscr; | |
244 | ||
245 | if(mpctl0) { | |
246 | CSCR |= CSCR_MPLL_RESTART; | |
247 | ||
6cbdc8c5 | 248 | /* Wait until MPLL is stabilized */ |
3c8cd0cc PP |
249 | while( CSCR & CSCR_MPLL_RESTART ); |
250 | ||
251 | imx_set_async_mode(); | |
252 | } | |
253 | ||
254 | local_irq_restore(flags); | |
255 | ||
256 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
257 | ||
258 | pr_debug(KERN_INFO "imx: set frequency %ld Hz, running from %s\n", | |
259 | freq, mpctl0? "MPLL": "SPLL"); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy) | |
265 | { | |
266 | printk(KERN_INFO "i.MX cpu freq change driver v1.0\n"); | |
267 | ||
268 | if (policy->cpu != 0) | |
269 | return -EINVAL; | |
270 | ||
271 | policy->cur = policy->min = policy->max = imx_get_speed(0); | |
3c8cd0cc PP |
272 | policy->cpuinfo.min_freq = 8000; |
273 | policy->cpuinfo.max_freq = 200000; | |
5225cd80 PP |
274 | /* Manual states, that PLL stabilizes in two CLK32 periods */ |
275 | policy->cpuinfo.transition_latency = 4 * 1000000000LL / CLK32; | |
3c8cd0cc PP |
276 | return 0; |
277 | } | |
278 | ||
279 | static struct cpufreq_driver imx_driver = { | |
280 | .flags = CPUFREQ_STICKY, | |
281 | .verify = imx_verify_speed, | |
282 | .target = imx_set_target, | |
283 | .get = imx_get_speed, | |
284 | .init = imx_cpufreq_driver_init, | |
285 | .name = "imx", | |
286 | }; | |
287 | ||
288 | static int __init imx_cpufreq_init(void) | |
289 | { | |
83b84c4e | 290 | bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1; |
3c8cd0cc PP |
291 | mpctl0_at_boot = 0; |
292 | ||
293 | if((CSCR & CSCR_MPEN) && | |
294 | ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE)) | |
295 | mpctl0_at_boot = MPCTL0; | |
296 | ||
297 | return cpufreq_register_driver(&imx_driver); | |
298 | } | |
299 | ||
300 | arch_initcall(imx_cpufreq_init); | |
301 |