[linux-2.6-block.git] / arch / arm / mach-imx / cpu.c

#include <linux/err.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>

#include "hardware.h"
#include "common.h"

unsigned int __mxc_cpu_type;
static unsigned int imx_soc_revision;

void mxc_set_cpu_type(unsigned int type)
{
	__mxc_cpu_type = type;
}

void imx_set_soc_revision(unsigned int rev)
{
	imx_soc_revision = rev;
}

unsigned int imx_get_soc_revision(void)
{
	return imx_soc_revision;
}

void imx_print_silicon_rev(const char *cpu, int srev)
{
	if (srev == IMX_CHIP_REVISION_UNKNOWN)
		pr_info("CPU identified as %s, unknown revision\n", cpu);
	else
		pr_info("CPU identified as %s, silicon rev %d.%d\n",
				cpu, (srev >> 4) & 0xf, srev & 0xf);
}

void __init imx_set_aips(void __iomem *base)
{
	unsigned int reg;
/*
 * Set all MPROTx to be non-bufferable, trusted for R/W,
 * not forced to user-mode.
 */
	imx_writel(0x77777777, base + 0x0);
	imx_writel(0x77777777, base + 0x4);

/*
 * Set all OPACRx to be non-bufferable, to not require
 * supervisor privilege level for access, allow for
 * write access and untrusted master access.
 */
	imx_writel(0x0, base + 0x40);
	imx_writel(0x0, base + 0x44);
	imx_writel(0x0, base + 0x48);
	imx_writel(0x0, base + 0x4C);
	reg = imx_readl(base + 0x50) & 0x00FFFFFF;
	imx_writel(reg, base + 0x50);
}

void __init imx_aips_allow_unprivileged_access(
		const char *compat)
{
	void __iomem *aips_base_addr;
	struct device_node *np;

	for_each_compatible_node(np, NULL, compat) {
		aips_base_addr = of_iomap(np, 0);
		imx_set_aips(aips_base_addr);
	}
}

struct device * __init imx_soc_device_init(void)
{
	struct soc_device_attribute *soc_dev_attr;
	struct soc_device *soc_dev;
	struct device_node *root;
	const char *soc_id;
	int ret;

	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	if (!soc_dev_attr)
		return NULL;

	soc_dev_attr->family = "Freescale i.MX";

	root = of_find_node_by_path("/");
	ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
	of_node_put(root);
	if (ret)
		goto free_soc;

	switch (__mxc_cpu_type) {
	case MXC_CPU_MX1:
		soc_id = "i.MX1";
		break;
	case MXC_CPU_MX21:
		soc_id = "i.MX21";
		break;
	case MXC_CPU_MX25:
		soc_id = "i.MX25";
		break;
	case MXC_CPU_MX27:
		soc_id = "i.MX27";
		break;
	case MXC_CPU_MX31:
		soc_id = "i.MX31";
		break;
	case MXC_CPU_MX35:
		soc_id = "i.MX35";
		break;
	case MXC_CPU_MX51:
		soc_id = "i.MX51";
		break;
	case MXC_CPU_MX53:
		soc_id = "i.MX53";
		break;
	case MXC_CPU_IMX6SL:
		soc_id = "i.MX6SL";
		break;
	case MXC_CPU_IMX6DL:
		soc_id = "i.MX6DL";
		break;
	case MXC_CPU_IMX6SX:
		soc_id = "i.MX6SX";
		break;
	case MXC_CPU_IMX6Q:
		soc_id = "i.MX6Q";
		break;
	case MXC_CPU_IMX6UL:
		soc_id = "i.MX6UL";
		break;
	case MXC_CPU_IMX7D:
		soc_id = "i.MX7D";
		break;
	default:
		soc_id = "Unknown";
	}
	soc_dev_attr->soc_id = soc_id;

	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
					   (imx_soc_revision >> 4) & 0xf,
					   imx_soc_revision & 0xf);
	if (!soc_dev_attr->revision)
		goto free_soc;

	soc_dev = soc_device_register(soc_dev_attr);
	if (IS_ERR(soc_dev))
		goto free_rev;

	return soc_device_to_device(soc_dev);

free_rev:
	kfree(soc_dev_attr->revision);
free_soc:
	kfree(soc_dev_attr);
	return NULL;
}
Commit	Line	Data
1ddd35be	1	#include <linux/err.h>
198016e1	2	#include <linux/module.h>
bb07d751	3	#include <linux/io.h>
a2887546	4	#include <linux/of.h>
e57e4ab5	5	#include <linux/of_address.h>
a2887546 SG	6	#include <linux/slab.h>
a2887546 SG	7	#include <linux/sys_soc.h>
50f2de61 SG	8
50f2de61 SG	9	#include "hardware.h"
e7feaaa7	10	#include "common.h"
198016e1 SH	11
198016e1 SH	12	unsigned int __mxc_cpu_type;
bfefdff8 SG	13	static unsigned int imx_soc_revision;
bfefdff8 SG	14
198016e1 SH	15	void mxc_set_cpu_type(unsigned int type)
	16	{
	17	__mxc_cpu_type = type;
	18	}
	19
bfefdff8 SG	20	void imx_set_soc_revision(unsigned int rev)
	21	{
	22	imx_soc_revision = rev;
	23	}
	24
	25	unsigned int imx_get_soc_revision(void)
	26	{
	27	return imx_soc_revision;
	28	}
	29
059e58f6 FE	30	void imx_print_silicon_rev(const char *cpu, int srev)
	31	{
	32	if (srev == IMX_CHIP_REVISION_UNKNOWN)
	33	pr_info("CPU identified as %s, unknown revision\n", cpu);
	34	else
	35	pr_info("CPU identified as %s, silicon rev %d.%d\n",
	36	cpu, (srev >> 4) & 0xf, srev & 0xf);
	37	}
bb07d751 FE	38
	39	void __init imx_set_aips(void __iomem *base)
	40	{
	41	unsigned int reg;
	42	/*
	43	* Set all MPROTx to be non-bufferable, trusted for R/W,
	44	* not forced to user-mode.
	45	*/
c553138f JB	46	imx_writel(0x77777777, base + 0x0);
c553138f JB	47	imx_writel(0x77777777, base + 0x4);
bb07d751 FE	48
	49	/*
	50	* Set all OPACRx to be non-bufferable, to not require
	51	* supervisor privilege level for access, allow for
	52	* write access and untrusted master access.
	53	*/
c553138f JB	54	imx_writel(0x0, base + 0x40);
	55	imx_writel(0x0, base + 0x44);
	56	imx_writel(0x0, base + 0x48);
	57	imx_writel(0x0, base + 0x4C);
	58	reg = imx_readl(base + 0x50) & 0x00FFFFFF;
	59	imx_writel(reg, base + 0x50);
bb07d751	60	}
a2887546	61
e57e4ab5 ST	62	void __init imx_aips_allow_unprivileged_access(
	63	const char *compat)
	64	{
	65	void __iomem *aips_base_addr;
	66	struct device_node *np;
	67
	68	for_each_compatible_node(np, NULL, compat) {
	69	aips_base_addr = of_iomap(np, 0);
	70	imx_set_aips(aips_base_addr);
	71	}
	72	}
	73
a2887546 SG	74	struct device * __init imx_soc_device_init(void)
	75	{
	76	struct soc_device_attribute *soc_dev_attr;
	77	struct soc_device *soc_dev;
	78	struct device_node *root;
	79	const char *soc_id;
	80	int ret;
	81
	82	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	83	if (!soc_dev_attr)
	84	return NULL;
	85
	86	soc_dev_attr->family = "Freescale i.MX";
	87
	88	root = of_find_node_by_path("/");
	89	ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
	90	of_node_put(root);
	91	if (ret)
	92	goto free_soc;
	93
	94	switch (__mxc_cpu_type) {
	95	case MXC_CPU_MX1:
	96	soc_id = "i.MX1";
	97	break;
	98	case MXC_CPU_MX21:
	99	soc_id = "i.MX21";
	100	break;
	101	case MXC_CPU_MX25:
	102	soc_id = "i.MX25";
	103	break;
	104	case MXC_CPU_MX27:
	105	soc_id = "i.MX27";
	106	break;
	107	case MXC_CPU_MX31:
	108	soc_id = "i.MX31";
	109	break;
	110	case MXC_CPU_MX35:
	111	soc_id = "i.MX35";
	112	break;
	113	case MXC_CPU_MX51:
	114	soc_id = "i.MX51";
	115	break;
	116	case MXC_CPU_MX53:
	117	soc_id = "i.MX53";
	118	break;
	119	case MXC_CPU_IMX6SL:
	120	soc_id = "i.MX6SL";
	121	break;
	122	case MXC_CPU_IMX6DL:
	123	soc_id = "i.MX6DL";
	124	break;
d9654dce SG	125	case MXC_CPU_IMX6SX:
	126	soc_id = "i.MX6SX";
	127	break;
a2887546 SG	128	case MXC_CPU_IMX6Q:
	129	soc_id = "i.MX6Q";
	130	break;
022d0716 FL	131	case MXC_CPU_IMX6UL:
	132	soc_id = "i.MX6UL";
	133	break;
5739b919 AH	134	case MXC_CPU_IMX7D:
	135	soc_id = "i.MX7D";
	136	break;
a2887546 SG	137	default:
	138	soc_id = "Unknown";
	139	}
	140	soc_dev_attr->soc_id = soc_id;
	141
	142	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
	143	(imx_soc_revision >> 4) & 0xf,
	144	imx_soc_revision & 0xf);
	145	if (!soc_dev_attr->revision)
	146	goto free_soc;
	147
	148	soc_dev = soc_device_register(soc_dev_attr);
	149	if (IS_ERR(soc_dev))
	150	goto free_rev;
	151
	152	return soc_device_to_device(soc_dev);
	153
	154	free_rev:
	155	kfree(soc_dev_attr->revision);
	156	free_soc:
	157	kfree(soc_dev_attr);
	158	return NULL;
	159	}