Merge branch 'for-4.5/lightnvm' of git://git.kernel.dk/linux-block
[linux-2.6-block.git] / arch / arm / mach-imx / cpu.c
CommitLineData
1ddd35be 1#include <linux/err.h>
198016e1 2#include <linux/module.h>
bb07d751 3#include <linux/io.h>
a2887546 4#include <linux/of.h>
e57e4ab5 5#include <linux/of_address.h>
a2887546
SG
6#include <linux/slab.h>
7#include <linux/sys_soc.h>
50f2de61
SG
8
9#include "hardware.h"
e7feaaa7 10#include "common.h"
198016e1
SH
11
12unsigned int __mxc_cpu_type;
13EXPORT_SYMBOL(__mxc_cpu_type);
14
bfefdff8
SG
15static unsigned int imx_soc_revision;
16
198016e1
SH
17void mxc_set_cpu_type(unsigned int type)
18{
19 __mxc_cpu_type = type;
20}
21
bfefdff8
SG
22void imx_set_soc_revision(unsigned int rev)
23{
24 imx_soc_revision = rev;
25}
26
27unsigned int imx_get_soc_revision(void)
28{
29 return imx_soc_revision;
30}
31
059e58f6
FE
32void imx_print_silicon_rev(const char *cpu, int srev)
33{
34 if (srev == IMX_CHIP_REVISION_UNKNOWN)
35 pr_info("CPU identified as %s, unknown revision\n", cpu);
36 else
37 pr_info("CPU identified as %s, silicon rev %d.%d\n",
38 cpu, (srev >> 4) & 0xf, srev & 0xf);
39}
bb07d751
FE
40
41void __init imx_set_aips(void __iomem *base)
42{
43 unsigned int reg;
44/*
45 * Set all MPROTx to be non-bufferable, trusted for R/W,
46 * not forced to user-mode.
47 */
48 __raw_writel(0x77777777, base + 0x0);
49 __raw_writel(0x77777777, base + 0x4);
50
51/*
52 * Set all OPACRx to be non-bufferable, to not require
53 * supervisor privilege level for access, allow for
54 * write access and untrusted master access.
55 */
56 __raw_writel(0x0, base + 0x40);
57 __raw_writel(0x0, base + 0x44);
58 __raw_writel(0x0, base + 0x48);
59 __raw_writel(0x0, base + 0x4C);
60 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
61 __raw_writel(reg, base + 0x50);
62}
a2887546 63
e57e4ab5
ST
64void __init imx_aips_allow_unprivileged_access(
65 const char *compat)
66{
67 void __iomem *aips_base_addr;
68 struct device_node *np;
69
70 for_each_compatible_node(np, NULL, compat) {
71 aips_base_addr = of_iomap(np, 0);
72 imx_set_aips(aips_base_addr);
73 }
74}
75
a2887546
SG
76struct device * __init imx_soc_device_init(void)
77{
78 struct soc_device_attribute *soc_dev_attr;
79 struct soc_device *soc_dev;
80 struct device_node *root;
81 const char *soc_id;
82 int ret;
83
84 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
85 if (!soc_dev_attr)
86 return NULL;
87
88 soc_dev_attr->family = "Freescale i.MX";
89
90 root = of_find_node_by_path("/");
91 ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
92 of_node_put(root);
93 if (ret)
94 goto free_soc;
95
96 switch (__mxc_cpu_type) {
97 case MXC_CPU_MX1:
98 soc_id = "i.MX1";
99 break;
100 case MXC_CPU_MX21:
101 soc_id = "i.MX21";
102 break;
103 case MXC_CPU_MX25:
104 soc_id = "i.MX25";
105 break;
106 case MXC_CPU_MX27:
107 soc_id = "i.MX27";
108 break;
109 case MXC_CPU_MX31:
110 soc_id = "i.MX31";
111 break;
112 case MXC_CPU_MX35:
113 soc_id = "i.MX35";
114 break;
115 case MXC_CPU_MX51:
116 soc_id = "i.MX51";
117 break;
118 case MXC_CPU_MX53:
119 soc_id = "i.MX53";
120 break;
121 case MXC_CPU_IMX6SL:
122 soc_id = "i.MX6SL";
123 break;
124 case MXC_CPU_IMX6DL:
125 soc_id = "i.MX6DL";
126 break;
d9654dce
SG
127 case MXC_CPU_IMX6SX:
128 soc_id = "i.MX6SX";
129 break;
a2887546
SG
130 case MXC_CPU_IMX6Q:
131 soc_id = "i.MX6Q";
132 break;
022d0716
FL
133 case MXC_CPU_IMX6UL:
134 soc_id = "i.MX6UL";
135 break;
5739b919
AH
136 case MXC_CPU_IMX7D:
137 soc_id = "i.MX7D";
138 break;
a2887546
SG
139 default:
140 soc_id = "Unknown";
141 }
142 soc_dev_attr->soc_id = soc_id;
143
144 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
145 (imx_soc_revision >> 4) & 0xf,
146 imx_soc_revision & 0xf);
147 if (!soc_dev_attr->revision)
148 goto free_soc;
149
150 soc_dev = soc_device_register(soc_dev_attr);
151 if (IS_ERR(soc_dev))
152 goto free_rev;
153
154 return soc_device_to_device(soc_dev);
155
156free_rev:
157 kfree(soc_dev_attr->revision);
158free_soc:
159 kfree(soc_dev_attr);
160 return NULL;
161}