[linux-2.6-block.git] / arch / arm / mach-imx / cpu.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/err.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>

#include "hardware.h"
#include "common.h"

unsigned int __mxc_cpu_type;
static unsigned int imx_soc_revision;

void mxc_set_cpu_type(unsigned int type)
{
	__mxc_cpu_type = type;
}

void imx_set_soc_revision(unsigned int rev)
{
	imx_soc_revision = rev;
}

unsigned int imx_get_soc_revision(void)
{
	return imx_soc_revision;
}

void imx_print_silicon_rev(const char *cpu, int srev)
{
	if (srev == IMX_CHIP_REVISION_UNKNOWN)
		pr_info("CPU identified as %s, unknown revision\n", cpu);
	else
		pr_info("CPU identified as %s, silicon rev %d.%d\n",
				cpu, (srev >> 4) & 0xf, srev & 0xf);
}

void __init imx_set_aips(void __iomem *base)
{
	unsigned int reg;
/*
 * Set all MPROTx to be non-bufferable, trusted for R/W,
 * not forced to user-mode.
 */
	imx_writel(0x77777777, base + 0x0);
	imx_writel(0x77777777, base + 0x4);

/*
 * Set all OPACRx to be non-bufferable, to not require
 * supervisor privilege level for access, allow for
 * write access and untrusted master access.
 */
	imx_writel(0x0, base + 0x40);
	imx_writel(0x0, base + 0x44);
	imx_writel(0x0, base + 0x48);
	imx_writel(0x0, base + 0x4C);
	reg = imx_readl(base + 0x50) & 0x00FFFFFF;
	imx_writel(reg, base + 0x50);
}

void __init imx_aips_allow_unprivileged_access(
		const char *compat)
{
	void __iomem *aips_base_addr;
	struct device_node *np;

	for_each_compatible_node(np, NULL, compat) {
		aips_base_addr = of_iomap(np, 0);
		WARN_ON(!aips_base_addr);
		imx_set_aips(aips_base_addr);
	}
}

struct device * __init imx_soc_device_init(void)
{
	struct soc_device_attribute *soc_dev_attr;
	struct soc_device *soc_dev;
	struct device_node *root;
	const char *soc_id;
	int ret;

	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	if (!soc_dev_attr)
		return NULL;

	soc_dev_attr->family = "Freescale i.MX";

	root = of_find_node_by_path("/");
	ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
	of_node_put(root);
	if (ret)
		goto free_soc;

	switch (__mxc_cpu_type) {
	case MXC_CPU_MX1:
		soc_id = "i.MX1";
		break;
	case MXC_CPU_MX21:
		soc_id = "i.MX21";
		break;
	case MXC_CPU_MX25:
		soc_id = "i.MX25";
		break;
	case MXC_CPU_MX27:
		soc_id = "i.MX27";
		break;
	case MXC_CPU_MX31:
		soc_id = "i.MX31";
		break;
	case MXC_CPU_MX35:
		soc_id = "i.MX35";
		break;
	case MXC_CPU_MX51:
		soc_id = "i.MX51";
		break;
	case MXC_CPU_MX53:
		soc_id = "i.MX53";
		break;
	case MXC_CPU_IMX6SL:
		soc_id = "i.MX6SL";
		break;
	case MXC_CPU_IMX6DL:
		soc_id = "i.MX6DL";
		break;
	case MXC_CPU_IMX6SX:
		soc_id = "i.MX6SX";
		break;
	case MXC_CPU_IMX6Q:
		soc_id = "i.MX6Q";
		break;
	case MXC_CPU_IMX6UL:
		soc_id = "i.MX6UL";
		break;
	case MXC_CPU_IMX6ULL:
		soc_id = "i.MX6ULL";
		break;
	case MXC_CPU_IMX6ULZ:
		soc_id = "i.MX6ULZ";
		break;
	case MXC_CPU_IMX6SLL:
		soc_id = "i.MX6SLL";
		break;
	case MXC_CPU_IMX7D:
		soc_id = "i.MX7D";
		break;
	case MXC_CPU_IMX7ULP:
		soc_id = "i.MX7ULP";
		break;
	default:
		soc_id = "Unknown";
	}
	soc_dev_attr->soc_id = soc_id;

	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
					   (imx_soc_revision >> 4) & 0xf,
					   imx_soc_revision & 0xf);
	if (!soc_dev_attr->revision)
		goto free_soc;

	soc_dev = soc_device_register(soc_dev_attr);
	if (IS_ERR(soc_dev))
		goto free_rev;

	return soc_device_to_device(soc_dev);

free_rev:
	kfree(soc_dev_attr->revision);
free_soc:
	kfree(soc_dev_attr);
	return NULL;
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1ddd35be	2	#include <linux/err.h>
198016e1	3	#include <linux/module.h>
bb07d751	4	#include <linux/io.h>
a2887546	5	#include <linux/of.h>
e57e4ab5	6	#include <linux/of_address.h>
a2887546 SG	7	#include <linux/slab.h>
a2887546 SG	8	#include <linux/sys_soc.h>
50f2de61 SG	9
50f2de61 SG	10	#include "hardware.h"
e7feaaa7	11	#include "common.h"
198016e1 SH	12
198016e1 SH	13	unsigned int __mxc_cpu_type;
bfefdff8 SG	14	static unsigned int imx_soc_revision;
bfefdff8 SG	15
198016e1 SH	16	void mxc_set_cpu_type(unsigned int type)
	17	{
	18	__mxc_cpu_type = type;
	19	}
	20
bfefdff8 SG	21	void imx_set_soc_revision(unsigned int rev)
	22	{
	23	imx_soc_revision = rev;
	24	}
	25
	26	unsigned int imx_get_soc_revision(void)
	27	{
	28	return imx_soc_revision;
	29	}
	30
059e58f6 FE	31	void imx_print_silicon_rev(const char *cpu, int srev)
	32	{
	33	if (srev == IMX_CHIP_REVISION_UNKNOWN)
	34	pr_info("CPU identified as %s, unknown revision\n", cpu);
	35	else
	36	pr_info("CPU identified as %s, silicon rev %d.%d\n",
	37	cpu, (srev >> 4) & 0xf, srev & 0xf);
	38	}
bb07d751 FE	39
	40	void __init imx_set_aips(void __iomem *base)
	41	{
	42	unsigned int reg;
	43	/*
	44	* Set all MPROTx to be non-bufferable, trusted for R/W,
	45	* not forced to user-mode.
	46	*/
c553138f JB	47	imx_writel(0x77777777, base + 0x0);
c553138f JB	48	imx_writel(0x77777777, base + 0x4);
bb07d751 FE	49
	50	/*
	51	* Set all OPACRx to be non-bufferable, to not require
	52	* supervisor privilege level for access, allow for
	53	* write access and untrusted master access.
	54	*/
c553138f JB	55	imx_writel(0x0, base + 0x40);
	56	imx_writel(0x0, base + 0x44);
	57	imx_writel(0x0, base + 0x48);
	58	imx_writel(0x0, base + 0x4C);
	59	reg = imx_readl(base + 0x50) & 0x00FFFFFF;
	60	imx_writel(reg, base + 0x50);
bb07d751	61	}
a2887546	62
e57e4ab5 ST	63	void __init imx_aips_allow_unprivileged_access(
	64	const char *compat)
	65	{
	66	void __iomem *aips_base_addr;
	67	struct device_node *np;
	68
	69	for_each_compatible_node(np, NULL, compat) {
	70	aips_base_addr = of_iomap(np, 0);
cff70654	71	WARN_ON(!aips_base_addr);
e57e4ab5 ST	72	imx_set_aips(aips_base_addr);
	73	}
	74	}
	75
a2887546 SG	76	struct device * __init imx_soc_device_init(void)
	77	{
	78	struct soc_device_attribute *soc_dev_attr;
	79	struct soc_device *soc_dev;
	80	struct device_node *root;
	81	const char *soc_id;
	82	int ret;
	83
	84	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	85	if (!soc_dev_attr)
	86	return NULL;
	87
	88	soc_dev_attr->family = "Freescale i.MX";
	89
	90	root = of_find_node_by_path("/");
	91	ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
	92	of_node_put(root);
	93	if (ret)
	94	goto free_soc;
	95
	96	switch (__mxc_cpu_type) {
	97	case MXC_CPU_MX1:
	98	soc_id = "i.MX1";
	99	break;
	100	case MXC_CPU_MX21:
	101	soc_id = "i.MX21";
	102	break;
	103	case MXC_CPU_MX25:
	104	soc_id = "i.MX25";
	105	break;
	106	case MXC_CPU_MX27:
	107	soc_id = "i.MX27";
	108	break;
	109	case MXC_CPU_MX31:
	110	soc_id = "i.MX31";
	111	break;
	112	case MXC_CPU_MX35:
	113	soc_id = "i.MX35";
	114	break;
	115	case MXC_CPU_MX51:
	116	soc_id = "i.MX51";
	117	break;
	118	case MXC_CPU_MX53:
	119	soc_id = "i.MX53";
	120	break;
	121	case MXC_CPU_IMX6SL:
	122	soc_id = "i.MX6SL";
	123	break;
	124	case MXC_CPU_IMX6DL:
	125	soc_id = "i.MX6DL";
	126	break;
d9654dce SG	127	case MXC_CPU_IMX6SX:
	128	soc_id = "i.MX6SX";
	129	break;
a2887546 SG	130	case MXC_CPU_IMX6Q:
	131	soc_id = "i.MX6Q";
	132	break;
022d0716 FL	133	case MXC_CPU_IMX6UL:
	134	soc_id = "i.MX6UL";
	135	break;
b3ea5757 LC	136	case MXC_CPU_IMX6ULL:
	137	soc_id = "i.MX6ULL";
	138	break;
c90dec00 AH	139	case MXC_CPU_IMX6ULZ:
	140	soc_id = "i.MX6ULZ";
	141	break;
dee5dee2 BP	142	case MXC_CPU_IMX6SLL:
	143	soc_id = "i.MX6SLL";
	144	break;
5739b919 AH	145	case MXC_CPU_IMX7D:
	146	soc_id = "i.MX7D";
	147	break;
de70d0e9 D	148	case MXC_CPU_IMX7ULP:
	149	soc_id = "i.MX7ULP";
	150	break;
a2887546 SG	151	default:
	152	soc_id = "Unknown";
	153	}
	154	soc_dev_attr->soc_id = soc_id;
	155
	156	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
	157	(imx_soc_revision >> 4) & 0xf,
	158	imx_soc_revision & 0xf);
	159	if (!soc_dev_attr->revision)
	160	goto free_soc;
	161
	162	soc_dev = soc_device_register(soc_dev_attr);
	163	if (IS_ERR(soc_dev))
	164	goto free_rev;
	165
	166	return soc_device_to_device(soc_dev);
	167
	168	free_rev:
	169	kfree(soc_dev_attr->revision);
	170	free_soc:
	171	kfree(soc_dev_attr);
	172	return NULL;
	173	}