Commit | Line | Data |
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2acd1b6f | 1 | /* |
e7b82d64 | 2 | * Copyright 2011-2013 Freescale Semiconductor, Inc. |
2acd1b6f SG |
3 | * Copyright 2011 Linaro Ltd. |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/clkdev.h> | |
263475d4 | 17 | #include <linux/delay.h> |
2acd1b6f SG |
18 | #include <linux/err.h> |
19 | #include <linux/io.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_irq.h> | |
e3372474 | 23 | |
2acd1b6f | 24 | #include "clk.h" |
e3372474 | 25 | #include "common.h" |
2acd1b6f | 26 | |
e7b82d64 AH |
27 | #define CCR 0x0 |
28 | #define BM_CCR_WB_COUNT (0x7 << 16) | |
263475d4 AH |
29 | #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) |
30 | #define BM_CCR_RBC_EN (0x1 << 27) | |
e7b82d64 | 31 | |
2acd1b6f SG |
32 | #define CCGR0 0x68 |
33 | #define CCGR1 0x6c | |
34 | #define CCGR2 0x70 | |
35 | #define CCGR3 0x74 | |
36 | #define CCGR4 0x78 | |
37 | #define CCGR5 0x7c | |
38 | #define CCGR6 0x80 | |
39 | #define CCGR7 0x84 | |
40 | ||
41 | #define CLPCR 0x54 | |
42 | #define BP_CLPCR_LPM 0 | |
43 | #define BM_CLPCR_LPM (0x3 << 0) | |
44 | #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) | |
45 | #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) | |
46 | #define BM_CLPCR_SBYOS (0x1 << 6) | |
47 | #define BM_CLPCR_DIS_REF_OSC (0x1 << 7) | |
48 | #define BM_CLPCR_VSTBY (0x1 << 8) | |
49 | #define BP_CLPCR_STBY_COUNT 9 | |
50 | #define BM_CLPCR_STBY_COUNT (0x3 << 9) | |
51 | #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) | |
52 | #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) | |
53 | #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) | |
54 | #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) | |
55 | #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) | |
56 | #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) | |
57 | #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) | |
58 | #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) | |
59 | #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) | |
60 | #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) | |
61 | #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) | |
62 | ||
e5f9dec8 SG |
63 | #define CGPR 0x64 |
64 | #define BM_CGPR_CHICKEN_BIT (0x1 << 17) | |
65 | ||
2acd1b6f SG |
66 | static void __iomem *ccm_base; |
67 | ||
e5f9dec8 SG |
68 | void imx6q_set_chicken_bit(void) |
69 | { | |
70 | u32 val = readl_relaxed(ccm_base + CGPR); | |
71 | ||
72 | val |= BM_CGPR_CHICKEN_BIT; | |
73 | writel_relaxed(val, ccm_base + CGPR); | |
74 | } | |
2acd1b6f | 75 | |
263475d4 AH |
76 | static void imx6q_enable_rbc(bool enable) |
77 | { | |
78 | u32 val; | |
79 | static bool last_rbc_mode; | |
80 | ||
81 | if (last_rbc_mode == enable) | |
82 | return; | |
83 | /* | |
84 | * need to mask all interrupts in GPC before | |
85 | * operating RBC configurations | |
86 | */ | |
87 | imx_gpc_mask_all(); | |
88 | ||
89 | /* configure RBC enable bit */ | |
90 | val = readl_relaxed(ccm_base + CCR); | |
91 | val &= ~BM_CCR_RBC_EN; | |
92 | val |= enable ? BM_CCR_RBC_EN : 0; | |
93 | writel_relaxed(val, ccm_base + CCR); | |
94 | ||
95 | /* configure RBC count */ | |
96 | val = readl_relaxed(ccm_base + CCR); | |
97 | val &= ~BM_CCR_RBC_BYPASS_COUNT; | |
98 | val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; | |
99 | writel(val, ccm_base + CCR); | |
100 | ||
101 | /* | |
102 | * need to delay at least 2 cycles of CKIL(32K) | |
103 | * due to hardware design requirement, which is | |
104 | * ~61us, here we use 65us for safe | |
105 | */ | |
106 | udelay(65); | |
107 | ||
108 | /* restore GPC interrupt mask settings */ | |
109 | imx_gpc_restore_all(); | |
110 | ||
111 | last_rbc_mode = enable; | |
112 | } | |
113 | ||
e7b82d64 AH |
114 | static void imx6q_enable_wb(bool enable) |
115 | { | |
116 | u32 val; | |
117 | static bool last_wb_mode; | |
118 | ||
119 | if (last_wb_mode == enable) | |
120 | return; | |
121 | ||
122 | /* configure well bias enable bit */ | |
123 | val = readl_relaxed(ccm_base + CLPCR); | |
124 | val &= ~BM_CLPCR_WB_PER_AT_LPM; | |
125 | val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; | |
126 | writel_relaxed(val, ccm_base + CLPCR); | |
127 | ||
128 | /* configure well bias count */ | |
129 | val = readl_relaxed(ccm_base + CCR); | |
130 | val &= ~BM_CCR_WB_COUNT; | |
131 | val |= enable ? BM_CCR_WB_COUNT : 0; | |
132 | writel_relaxed(val, ccm_base + CCR); | |
133 | ||
134 | last_wb_mode = enable; | |
135 | } | |
136 | ||
2acd1b6f SG |
137 | int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) |
138 | { | |
139 | u32 val = readl_relaxed(ccm_base + CLPCR); | |
140 | ||
141 | val &= ~BM_CLPCR_LPM; | |
142 | switch (mode) { | |
143 | case WAIT_CLOCKED: | |
e7b82d64 | 144 | imx6q_enable_wb(false); |
263475d4 | 145 | imx6q_enable_rbc(false); |
2acd1b6f SG |
146 | break; |
147 | case WAIT_UNCLOCKED: | |
148 | val |= 0x1 << BP_CLPCR_LPM; | |
e5f9dec8 | 149 | val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; |
2acd1b6f SG |
150 | break; |
151 | case STOP_POWER_ON: | |
152 | val |= 0x2 << BP_CLPCR_LPM; | |
153 | break; | |
154 | case WAIT_UNCLOCKED_POWER_OFF: | |
155 | val |= 0x1 << BP_CLPCR_LPM; | |
156 | val &= ~BM_CLPCR_VSTBY; | |
157 | val &= ~BM_CLPCR_SBYOS; | |
158 | break; | |
159 | case STOP_POWER_OFF: | |
160 | val |= 0x2 << BP_CLPCR_LPM; | |
161 | val |= 0x3 << BP_CLPCR_STBY_COUNT; | |
162 | val |= BM_CLPCR_VSTBY; | |
163 | val |= BM_CLPCR_SBYOS; | |
e7b82d64 | 164 | imx6q_enable_wb(true); |
263475d4 | 165 | imx6q_enable_rbc(true); |
2acd1b6f SG |
166 | break; |
167 | default: | |
168 | return -EINVAL; | |
169 | } | |
170 | ||
171 | writel_relaxed(val, ccm_base + CLPCR); | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; | |
177 | static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; | |
178 | static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; | |
179 | static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", }; | |
180 | static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; | |
181 | static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; | |
182 | static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", }; | |
183 | static const char *audio_sels[] = { "pll4_audio", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; | |
184 | static const char *gpu_axi_sels[] = { "axi", "ahb", }; | |
185 | static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; | |
186 | static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; | |
187 | static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", }; | |
188 | static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; | |
e8094b2c | 189 | static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; |
2acd1b6f SG |
190 | static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; |
191 | static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
192 | static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
193 | static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
194 | static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
195 | static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; | |
196 | static const char *pcie_axi_sels[] = { "axi", "ahb", }; | |
197 | static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio", }; | |
198 | static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; | |
199 | static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; | |
200 | static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; | |
201 | static const char *vdo_axi_sels[] = { "axi", "ahb", }; | |
202 | static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; | |
203 | static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video", | |
204 | "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", | |
205 | "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", }; | |
206 | ||
2acd1b6f SG |
207 | enum mx6q_clks { |
208 | dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, | |
209 | pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m, | |
210 | pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw, | |
211 | periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel, | |
212 | esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel, | |
213 | gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel, | |
214 | ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel, | |
215 | ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, | |
216 | ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel, | |
217 | usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel, | |
218 | emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2, | |
219 | periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf, | |
220 | asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root, | |
221 | gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf, | |
222 | ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre, | |
223 | ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf, | |
224 | ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf, | |
225 | usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf, | |
226 | emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf, | |
227 | mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial, | |
228 | can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet, | |
229 | esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, | |
230 | hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, | |
231 | ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, | |
77ac32ad | 232 | mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, |
2acd1b6f SG |
233 | gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, |
234 | ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, | |
235 | usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, | |
13861701 | 236 | pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, |
16339464 | 237 | ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, |
a5120e89 PC |
238 | sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, |
239 | usbphy2_gate, clk_max | |
2acd1b6f SG |
240 | }; |
241 | ||
242 | static struct clk *clk[clk_max]; | |
0e87e043 | 243 | static struct clk_onecell_data clk_data; |
2acd1b6f | 244 | |
b0286f20 | 245 | static enum mx6q_clks const clks_init_on[] __initconst = { |
39581662 | 246 | mmdc_ch0_axi, rom, pll1_sys, |
b0286f20 RZ |
247 | }; |
248 | ||
7a04092c SH |
249 | static struct clk_div_table clk_enet_ref_table[] = { |
250 | { .val = 0, .div = 20, }, | |
251 | { .val = 1, .div = 10, }, | |
252 | { .val = 2, .div = 5, }, | |
253 | { .val = 3, .div = 4, }, | |
254 | }; | |
255 | ||
2acd1b6f SG |
256 | int __init mx6q_clocks_init(void) |
257 | { | |
258 | struct device_node *np; | |
259 | void __iomem *base; | |
2acd1b6f SG |
260 | int i, irq; |
261 | ||
262 | clk[dummy] = imx_clk_fixed("dummy", 0); | |
263 | ||
264 | /* retrieve the freqency of fixed clocks from device tree */ | |
265 | for_each_compatible_node(np, NULL, "fixed-clock") { | |
266 | u32 rate; | |
267 | if (of_property_read_u32(np, "clock-frequency", &rate)) | |
268 | continue; | |
269 | ||
270 | if (of_device_is_compatible(np, "fsl,imx-ckil")) | |
271 | clk[ckil] = imx_clk_fixed("ckil", rate); | |
272 | else if (of_device_is_compatible(np, "fsl,imx-ckih1")) | |
273 | clk[ckih] = imx_clk_fixed("ckih", rate); | |
274 | else if (of_device_is_compatible(np, "fsl,imx-osc")) | |
275 | clk[osc] = imx_clk_fixed("osc", rate); | |
276 | } | |
277 | ||
278 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); | |
279 | base = of_iomap(np, 0); | |
280 | WARN_ON(!base); | |
281 | ||
2b254693 SH |
282 | /* type name parent_name base div_mask */ |
283 | clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); | |
284 | clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); | |
285 | clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); | |
286 | clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); | |
287 | clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); | |
288 | clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); | |
289 | clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); | |
290 | clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0); | |
2acd1b6f | 291 | |
a5120e89 PC |
292 | /* |
293 | * Bit 20 is the reserved and read-only bit, we do this only for: | |
294 | * - Do nothing for usbphy clk_enable/disable | |
295 | * - Keep refcount when do usbphy clk_enable/disable, in that case, | |
296 | * the clk framework may need to enable/disable usbphy's parent | |
297 | */ | |
298 | clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); | |
299 | clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); | |
300 | ||
301 | /* | |
302 | * usbphy*_gate needs to be on after system boots up, and software | |
303 | * never needs to control it anymore. | |
304 | */ | |
305 | clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); | |
306 | clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); | |
7571d283 | 307 | |
7a04092c SH |
308 | clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); |
309 | clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); | |
310 | ||
311 | clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); | |
312 | clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); | |
313 | ||
314 | clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, | |
315 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, | |
316 | &imx_ccm_lock); | |
317 | ||
2acd1b6f SG |
318 | /* name parent_name reg idx */ |
319 | clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); | |
320 | clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); | |
321 | clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); | |
322 | clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); | |
323 | clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); | |
324 | clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); | |
325 | clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); | |
326 | ||
327 | /* name parent_name mult div */ | |
328 | clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); | |
329 | clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); | |
330 | clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); | |
331 | clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); | |
332 | clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); | |
333 | ||
334 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm"); | |
335 | base = of_iomap(np, 0); | |
336 | WARN_ON(!base); | |
337 | ccm_base = base; | |
338 | ||
339 | /* name reg shift width parent_names num_parents */ | |
340 | clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); | |
341 | clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); | |
342 | clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); | |
343 | clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); | |
344 | clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); | |
345 | clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); | |
346 | clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); | |
347 | clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
348 | clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
349 | clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
350 | clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); | |
351 | clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); | |
352 | clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); | |
353 | clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); | |
354 | clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); | |
355 | clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | |
356 | clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | |
d19dacb7 PZ |
357 | clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); |
358 | clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); | |
2acd1b6f SG |
359 | clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); |
360 | clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); | |
361 | clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); | |
362 | clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); | |
363 | clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels)); | |
364 | clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels)); | |
365 | clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels)); | |
366 | clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels)); | |
367 | clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); | |
368 | clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); | |
369 | clk[ssi1_sel] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | |
370 | clk[ssi2_sel] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | |
371 | clk[ssi3_sel] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | |
372 | clk[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
373 | clk[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
374 | clk[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
375 | clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
376 | clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); | |
377 | clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels)); | |
378 | clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels)); | |
379 | clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); | |
380 | clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); | |
381 | clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); | |
382 | ||
383 | /* name reg shift width busy: reg, shift parent_names num_parents */ | |
384 | clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); | |
385 | clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); | |
386 | ||
387 | /* name parent_name reg shift width */ | |
388 | clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); | |
389 | clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); | |
390 | clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); | |
391 | clk[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6); | |
392 | clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); | |
393 | clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); | |
394 | clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); | |
395 | clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); | |
396 | clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); | |
397 | clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); | |
398 | clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); | |
399 | clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); | |
400 | clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); | |
401 | clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); | |
402 | clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); | |
403 | clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); | |
404 | clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); | |
16339464 | 405 | clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); |
d19dacb7 | 406 | clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); |
16339464 | 407 | clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); |
d19dacb7 | 408 | clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); |
2acd1b6f SG |
409 | clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); |
410 | clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); | |
411 | clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); | |
412 | clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); | |
413 | clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); | |
414 | clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); | |
415 | clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); | |
416 | clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); | |
417 | clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); | |
418 | clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); | |
419 | clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); | |
420 | clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); | |
421 | clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); | |
422 | clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); | |
423 | clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); | |
424 | clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); | |
425 | clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); | |
426 | clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); | |
427 | clk[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3); | |
428 | clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3); | |
429 | clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); | |
430 | clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); | |
431 | ||
432 | /* name parent_name reg shift width busy: reg, shift */ | |
433 | clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); | |
434 | clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); | |
435 | clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); | |
436 | clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); | |
437 | clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); | |
438 | ||
439 | /* name parent_name reg shift */ | |
10a81378 | 440 | clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); |
2acd1b6f SG |
441 | clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); |
442 | clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); | |
443 | clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); | |
444 | clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); | |
445 | clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); | |
446 | clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); | |
447 | clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); | |
448 | clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); | |
449 | clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); | |
450 | clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); | |
451 | clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); | |
452 | clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16); | |
453 | clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); | |
454 | clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); | |
455 | clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); | |
456 | clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); | |
457 | clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); | |
458 | clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); | |
459 | clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); | |
460 | clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); | |
461 | clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); | |
462 | clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); | |
463 | clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); | |
464 | clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); | |
465 | clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); | |
466 | clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); | |
467 | clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); | |
468 | clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); | |
469 | clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); | |
470 | clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); | |
471 | clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); | |
472 | clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); | |
13861701 | 473 | clk[mlb] = imx_clk_gate2("mlb", "pll8_mlb", base + 0x74, 18); |
2acd1b6f SG |
474 | clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); |
475 | clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); | |
476 | clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); | |
477 | clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); | |
478 | clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); | |
77ac32ad | 479 | clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); |
2acd1b6f SG |
480 | clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); |
481 | clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); | |
482 | clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); | |
483 | clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); | |
484 | clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); | |
485 | clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); | |
486 | clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); | |
487 | clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); | |
5ae95aef | 488 | clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); |
2acd1b6f SG |
489 | clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); |
490 | clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); | |
491 | clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); | |
0987b598 RZ |
492 | clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); |
493 | clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); | |
494 | clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); | |
2acd1b6f SG |
495 | clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); |
496 | clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); | |
497 | clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); | |
498 | clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); | |
499 | clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); | |
500 | clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); | |
501 | clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); | |
502 | clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); | |
503 | clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); | |
504 | clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); | |
505 | ||
506 | for (i = 0; i < ARRAY_SIZE(clk); i++) | |
507 | if (IS_ERR(clk[i])) | |
508 | pr_err("i.MX6q clk %d: register failed with %ld\n", | |
509 | i, PTR_ERR(clk[i])); | |
510 | ||
0e87e043 SG |
511 | clk_data.clks = clk; |
512 | clk_data.clk_num = ARRAY_SIZE(clk); | |
513 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
514 | ||
2acd1b6f SG |
515 | clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); |
516 | clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); | |
a258561d RZ |
517 | clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); |
518 | clk_register_clkdev(clk[ahb], "ahb", NULL); | |
519 | clk_register_clkdev(clk[cko1], "cko1", NULL); | |
d90df978 | 520 | clk_register_clkdev(clk[arm], NULL, "cpu0"); |
2acd1b6f | 521 | |
cc7887c3 HS |
522 | /* |
523 | * The gpmi needs 100MHz frequency in the EDO/Sync mode, | |
524 | * We can not get the 100MHz from the pll2_pfd0_352m. | |
525 | * So choose pll2_pfd2_396m as enfc_sel's parent. | |
526 | */ | |
527 | clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); | |
528 | ||
b0286f20 RZ |
529 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
530 | clk_prepare_enable(clk[clks_init_on[i]]); | |
2acd1b6f | 531 | |
a5120e89 PC |
532 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { |
533 | clk_prepare_enable(clk[usbphy1_gate]); | |
534 | clk_prepare_enable(clk[usbphy2_gate]); | |
535 | } | |
536 | ||
83ae2098 SG |
537 | /* Set initial power mode */ |
538 | imx6q_set_lpm(WAIT_CLOCKED); | |
539 | ||
2acd1b6f SG |
540 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); |
541 | base = of_iomap(np, 0); | |
542 | WARN_ON(!base); | |
543 | irq = irq_of_parse_and_map(np, 0); | |
2cfb4518 | 544 | mxc_timer_init(base, irq); |
2acd1b6f SG |
545 | |
546 | return 0; | |
547 | } |