[linux-2.6-block.git] / arch / arm / mach-imx / clk-imx21.c

/*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/clkdev.h>
#include <linux/err.h>

#include <mach/hardware.h>
#include <mach/common.h>
#include "clk.h"

#define IO_ADDR_CCM(off)	(MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))

/* Register offsets */
#define CCM_CSCR		IO_ADDR_CCM(0x0)
#define CCM_MPCTL0		IO_ADDR_CCM(0x4)
#define CCM_MPCTL1		IO_ADDR_CCM(0x8)
#define CCM_SPCTL0		IO_ADDR_CCM(0xc)
#define CCM_SPCTL1		IO_ADDR_CCM(0x10)
#define CCM_OSC26MCTL		IO_ADDR_CCM(0x14)
#define CCM_PCDR0		IO_ADDR_CCM(0x18)
#define CCM_PCDR1		IO_ADDR_CCM(0x1c)
#define CCM_PCCR0		IO_ADDR_CCM(0x20)
#define CCM_PCCR1		IO_ADDR_CCM(0x24)
#define CCM_CCSR		IO_ADDR_CCM(0x28)
#define CCM_PMCTL		IO_ADDR_CCM(0x2c)
#define CCM_PMCOUNT		IO_ADDR_CCM(0x30)
#define CCM_WKGDCTL		IO_ADDR_CCM(0x34)

static const char *mpll_sel_clks[] = { "fpm", "ckih", };
static const char *spll_sel_clks[] = { "fpm", "ckih", };

enum imx21_clks {
	ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
	per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
	uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
	pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
	lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
	per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
	ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
	emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
	gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
};

static struct clk *clk[clk_max];

/*
 * must be called very early to get information about the
 * available clock rate when the timer framework starts
 */
int __init mx21_clocks_init(unsigned long lref, unsigned long href)
{
	int i;

	clk[ckil] = imx_clk_fixed("ckil", lref);
	clk[ckih] = imx_clk_fixed("ckih", href);
	clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
	clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
			ARRAY_SIZE(mpll_sel_clks));
	clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
			ARRAY_SIZE(spll_sel_clks));
	clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
	clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
	clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
	clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
	clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
	clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
	clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
	clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
	clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
	clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
	clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
	clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
	clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
	clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
	clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
	clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
	clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
	clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
	clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
	clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
	clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
	clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
	clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
	clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
	clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
	clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
	clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
	clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
	clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
	clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
	clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
	clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
	clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
	clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
	clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
	clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
	clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
	clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
	clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
	clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
	clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
	clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
	clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
	clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
	clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
	clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);

	for (i = 0; i < ARRAY_SIZE(clk); i++)
		if (IS_ERR(clk[i]))
			pr_err("i.MX21 clk %d: register failed with %ld\n",
				i, PTR_ERR(clk[i]));

	clk_register_clkdev(clk[per1], "per1", NULL);
	clk_register_clkdev(clk[per2], "per2", NULL);
	clk_register_clkdev(clk[per3], "per3", NULL);
	clk_register_clkdev(clk[per4], "per4", NULL);
	clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
	clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
	clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
	clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
	clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
	clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
	clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
	clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
	clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
	clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
	clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
	clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
	clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
	clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
	clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0");
	clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
	clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
	clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
	clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
	clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
	clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
	clk_register_clkdev(clk[per3], "per", "imx-fb.0");
	clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0");
	clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx-fb.0");
	clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
	clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
	clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand.0");
	clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx-dma");
	clk_register_clkdev(clk[dma_gate], "ipg", "imx-dma");
	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
	clk_register_clkdev(clk[i2c_gate], NULL, "imx-i2c.0");
	clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
	clk_register_clkdev(clk[brom_gate], "brom", NULL);
	clk_register_clkdev(clk[emma_gate], "emma", NULL);
	clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
	clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
	clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
	clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
	clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
	clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
	clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
	clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);

	mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);

	return 0;
}
Commit	Line	Data
93421e42 SH	1	/*
	2	* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	* Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	18	* MA 02110-1301, USA.
	19	*/
	20
	21	#include <linux/clk.h>
	22	#include <linux/clkdev.h>
	23	#include <linux/clk-provider.h>
	24	#include <linux/io.h>
	25	#include <linux/module.h>
	26	#include <linux/clkdev.h>
	27	#include <linux/err.h>
	28
	29	#include <mach/hardware.h>
	30	#include <mach/common.h>
	31	#include "clk.h"
	32
	33	#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
	34
	35	/* Register offsets */
	36	#define CCM_CSCR IO_ADDR_CCM(0x0)
	37	#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
	38	#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
	39	#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
	40	#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
	41	#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
	42	#define CCM_PCDR0 IO_ADDR_CCM(0x18)
	43	#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
	44	#define CCM_PCCR0 IO_ADDR_CCM(0x20)
	45	#define CCM_PCCR1 IO_ADDR_CCM(0x24)
	46	#define CCM_CCSR IO_ADDR_CCM(0x28)
	47	#define CCM_PMCTL IO_ADDR_CCM(0x2c)
	48	#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
	49	#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
	50
	51	static const char *mpll_sel_clks[] = { "fpm", "ckih", };
	52	static const char *spll_sel_clks[] = { "fpm", "ckih", };
	53
	54	enum imx21_clks {
	55	ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
	56	per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
	57	uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
	58	pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
	59	lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
	60	per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
	61	ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
	62	emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
	63	gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
	64	};
65
66	static struct clk *clk[clk_max];
67
68	/*
69	* must be called very early to get information about the
70	* available clock rate when the timer framework starts
71	*/
72	int __init mx21_clocks_init(unsigned long lref, unsigned long href)
73	{
74	int i;
75
76	clk[ckil] = imx_clk_fixed("ckil", lref);
77	clk[ckih] = imx_clk_fixed("ckih", href);
78	clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
79	clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
80	ARRAY_SIZE(mpll_sel_clks));
81	clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
82	ARRAY_SIZE(spll_sel_clks));
83	clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
84	clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
85	clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
86	clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
87	clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
88	clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
89	clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
90	clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
91	clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
92	clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
93	clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
94	clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
95	clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
96	clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
97	clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
98	clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
99	clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
100	clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
101	clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
102	clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
103	clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
104	clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
105	clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
106	clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
107	clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
108	clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
109	clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
110	clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
111	clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
112	clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
113	clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
114	clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
115	clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
116	clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
117	clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
118	clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
119	clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
120	clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
121	clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
122	clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
123	clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
124	clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
125	clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
126	clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
127	clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
128	clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
129
130	for (i = 0; i < ARRAY_SIZE(clk); i++)
131	if (IS_ERR(clk[i]))
132	pr_err("i.MX21 clk %d: register failed with %ld\n",
133	i, PTR_ERR(clk[i]));
134
135	clk_register_clkdev(clk[per1], "per1", NULL);
136	clk_register_clkdev(clk[per2], "per2", NULL);
137	clk_register_clkdev(clk[per3], "per3", NULL);
138	clk_register_clkdev(clk[per4], "per4", NULL);
139	clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
140	clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
141	clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
142	clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
143	clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
144	clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
145	clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
146	clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
147	clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
148	clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
149	clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
150	clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
151	clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
152	clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
153	clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0");
154	clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
155	clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
156	clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
157	clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
158	clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
159	clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
160	clk_register_clkdev(clk[per3], "per", "imx-fb.0");
161	clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0");
162	clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx-fb.0");
163	clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
164	clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
165	clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand.0");
166	clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx-dma");
167	clk_register_clkdev(clk[dma_gate], "ipg", "imx-dma");
168	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
169	clk_register_clkdev(clk[i2c_gate], NULL, "imx-i2c.0");
170	clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
171	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
172	clk_register_clkdev(clk[brom_gate], "brom", NULL);
173	clk_register_clkdev(clk[emma_gate], "emma", NULL);
174	clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
175	clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
176	clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
177	clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
178	clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
179	clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
180	clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
181	clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
182
2cfb4518 SH	183	mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
2cfb4518 SH	184
93421e42 SH	185	return 0;
93421e42 SH	186	}