[linux-2.6-block.git] / arch / arm / mach-hisi / platsmp.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2013 Linaro Ltd.
 * Copyright (c) 2013 HiSilicon Limited.
 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
 */
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/delay.h>

#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include <asm/mach/map.h>

#include "core.h"

#define HIX5HD2_BOOT_ADDRESS		0xffff0000

static void __iomem *ctrl_base;

void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
{
	cpu = cpu_logical_map(cpu);
	if (!cpu || !ctrl_base)
		return;
	writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2));
}

int hi3xxx_get_cpu_jump(int cpu)
{
	cpu = cpu_logical_map(cpu);
	if (!cpu || !ctrl_base)
		return 0;
	return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
}

static void __init hisi_enable_scu_a9(void)
{
	unsigned long base = 0;
	void __iomem *scu_base = NULL;

	if (scu_a9_has_base()) {
		base = scu_a9_get_base();
		scu_base = ioremap(base, SZ_4K);
		if (!scu_base) {
			pr_err("ioremap(scu_base) failed\n");
			return;
		}
		scu_enable(scu_base);
		iounmap(scu_base);
	}
}

static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
{
	struct device_node *np = NULL;
	u32 offset = 0;

	hisi_enable_scu_a9();
	if (!ctrl_base) {
		np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
		if (!np) {
			pr_err("failed to find hisilicon,sysctrl node\n");
			return;
		}
		ctrl_base = of_iomap(np, 0);
		if (!ctrl_base) {
			of_node_put(np);
			pr_err("failed to map address\n");
			return;
		}
		if (of_property_read_u32(np, "smp-offset", &offset) < 0) {
			of_node_put(np);
			pr_err("failed to find smp-offset property\n");
			return;
		}
		ctrl_base += offset;
		of_node_put(np);
	}
}

static int hi3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	hi3xxx_set_cpu(cpu, true);
	hi3xxx_set_cpu_jump(cpu, secondary_startup);
	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
	return 0;
}

static const struct smp_operations hi3xxx_smp_ops __initconst = {
	.smp_prepare_cpus	= hi3xxx_smp_prepare_cpus,
	.smp_boot_secondary	= hi3xxx_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_die		= hi3xxx_cpu_die,
	.cpu_kill		= hi3xxx_cpu_kill,
#endif
};

static void __init hisi_common_smp_prepare_cpus(unsigned int max_cpus)
{
	hisi_enable_scu_a9();
}

static void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
{
	void __iomem *virt;

	virt = ioremap(start_addr, PAGE_SIZE);

	writel_relaxed(0xe51ff004, virt);	/* ldr pc, [pc, #-4] */
	writel_relaxed(jump_addr, virt + 4);	/* pc jump phy address */
	iounmap(virt);
}

static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	phys_addr_t jumpaddr;

	jumpaddr = __pa_symbol(secondary_startup);
	hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
	hix5hd2_set_cpu(cpu, true);
	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
	return 0;
}


static const struct smp_operations hix5hd2_smp_ops __initconst = {
	.smp_prepare_cpus	= hisi_common_smp_prepare_cpus,
	.smp_boot_secondary	= hix5hd2_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_die		= hix5hd2_cpu_die,
#endif
};


#define SC_SCTL_REMAP_CLR      0x00000100
#define HIP01_BOOT_ADDRESS     0x80000000
#define REG_SC_CTRL            0x000

static void hip01_set_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
{
	void __iomem *virt;

	virt = phys_to_virt(start_addr);

	writel_relaxed(0xe51ff004, virt);
	writel_relaxed(jump_addr, virt + 4);
}

static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	phys_addr_t jumpaddr;
	unsigned int remap_reg_value = 0;
	struct device_node *node;


	jumpaddr = __pa_symbol(secondary_startup);
	hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);

	node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
	if (WARN_ON(!node))
		return -1;
	ctrl_base = of_iomap(node, 0);
	of_node_put(node);

	/* set the secondary core boot from DDR */
	remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL);
	barrier();
	remap_reg_value |= SC_SCTL_REMAP_CLR;
	barrier();
	writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL);

	hip01_set_cpu(cpu, true);

	return 0;
}

static const struct smp_operations hip01_smp_ops __initconst = {
	.smp_prepare_cpus       = hisi_common_smp_prepare_cpus,
	.smp_boot_secondary     = hip01_boot_secondary,
};

CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3620-smp", &hi3xxx_smp_ops);
CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);
CPU_METHOD_OF_DECLARE(hip01_smp, "hisilicon,hip01-smp", &hip01_smp_ops);
Commit	Line	Data
75a6faf6	1	// SPDX-License-Identifier: GPL-2.0-only
a9434e96 KH	2	/*
a9434e96 KH	3	* Copyright (c) 2013 Linaro Ltd.
c1ce9d80	4	* Copyright (c) 2013 HiSilicon Limited.
a9434e96	5	* Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
a9434e96 KH	6	*/
	7	#include <linux/smp.h>
	8	#include <linux/io.h>
	9	#include <linux/of_address.h>
7fda91e7	10	#include <linux/delay.h>
a9434e96 KH	11
	12	#include <asm/cacheflush.h>
	13	#include <asm/smp_plat.h>
	14	#include <asm/smp_scu.h>
7fda91e7	15	#include <asm/mach/map.h>
a9434e96 KH	16
	17	#include "core.h"
	18
06cc5c1d HY	19	#define HIX5HD2_BOOT_ADDRESS 0xffff0000
06cc5c1d HY	20
a9434e96 KH	21	static void __iomem *ctrl_base;
	22
	23	void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
	24	{
	25	cpu = cpu_logical_map(cpu);
	26	if (!cpu \|\| !ctrl_base)
	27	return;
64fc2a94	28	writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2));
a9434e96 KH	29	}
	30
	31	int hi3xxx_get_cpu_jump(int cpu)
	32	{
	33	cpu = cpu_logical_map(cpu);
	34	if (!cpu \|\| !ctrl_base)
	35	return 0;
	36	return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
	37	}
	38
06cc5c1d	39	static void __init hisi_enable_scu_a9(void)
a9434e96	40	{
a9434e96	41	unsigned long base = 0;
a9434e96 KH	42	void __iomem *scu_base = NULL;
	43
	44	if (scu_a9_has_base()) {
	45	base = scu_a9_get_base();
	46	scu_base = ioremap(base, SZ_4K);
	47	if (!scu_base) {
	48	pr_err("ioremap(scu_base) failed\n");
	49	return;
	50	}
	51	scu_enable(scu_base);
	52	iounmap(scu_base);
	53	}
06cc5c1d HY	54	}
	55
	56	static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
	57	{
	58	struct device_node *np = NULL;
	59	u32 offset = 0;
	60
	61	hisi_enable_scu_a9();
a9434e96 KH	62	if (!ctrl_base) {
	63	np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
	64	if (!np) {
	65	pr_err("failed to find hisilicon,sysctrl node\n");
	66	return;
	67	}
	68	ctrl_base = of_iomap(np, 0);
	69	if (!ctrl_base) {
9bc72e47	70	of_node_put(np);
a9434e96 KH	71	pr_err("failed to map address\n");
	72	return;
	73	}
	74	if (of_property_read_u32(np, "smp-offset", &offset) < 0) {
9bc72e47	75	of_node_put(np);
a9434e96 KH	76	pr_err("failed to find smp-offset property\n");
	77	return;
	78	}
	79	ctrl_base += offset;
9bc72e47	80	of_node_put(np);
a9434e96 KH	81	}
	82	}
	83
	84	static int hi3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
	85	{
22bae429	86	hi3xxx_set_cpu(cpu, true);
a9434e96 KH	87	hi3xxx_set_cpu_jump(cpu, secondary_startup);
	88	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
	89	return 0;
	90	}
	91
75305275	92	static const struct smp_operations hi3xxx_smp_ops __initconst = {
a9434e96 KH	93	.smp_prepare_cpus = hi3xxx_smp_prepare_cpus,
a9434e96 KH	94	.smp_boot_secondary = hi3xxx_boot_secondary,
22bae429 ZG	95	#ifdef CONFIG_HOTPLUG_CPU
	96	.cpu_die = hi3xxx_cpu_die,
	97	.cpu_kill = hi3xxx_cpu_kill,
	98	#endif
a9434e96	99	};
06cc5c1d	100
e243f943	101	static void __init hisi_common_smp_prepare_cpus(unsigned int max_cpus)
06cc5c1d HY	102	{
	103	hisi_enable_scu_a9();
	104	}
	105
09ca62f5	106	static void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
06cc5c1d HY	107	{
	108	void __iomem *virt;
	109
	110	virt = ioremap(start_addr, PAGE_SIZE);
	111
d2057bbb	112	writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */
06cc5c1d HY	113	writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */
	114	iounmap(virt);
	115	}
	116
	117	static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
	118	{
	119	phys_addr_t jumpaddr;
	120
64fc2a94	121	jumpaddr = __pa_symbol(secondary_startup);
06cc5c1d HY	122	hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
	123	hix5hd2_set_cpu(cpu, true);
	124	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
	125	return 0;
	126	}
	127
	128
75305275	129	static const struct smp_operations hix5hd2_smp_ops __initconst = {
e243f943	130	.smp_prepare_cpus = hisi_common_smp_prepare_cpus,
06cc5c1d HY	131	.smp_boot_secondary = hix5hd2_boot_secondary,
	132	#ifdef CONFIG_HOTPLUG_CPU
	133	.cpu_die = hix5hd2_cpu_die,
	134	#endif
	135	};
c2fff85e	136
7fda91e7 WL	137
	138	#define SC_SCTL_REMAP_CLR 0x00000100
	139	#define HIP01_BOOT_ADDRESS 0x80000000
	140	#define REG_SC_CTRL 0x000
	141
09ca62f5	142	static void hip01_set_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
7fda91e7 WL	143	{
	144	void __iomem *virt;
	145
	146	virt = phys_to_virt(start_addr);
	147
	148	writel_relaxed(0xe51ff004, virt);
	149	writel_relaxed(jump_addr, virt + 4);
	150	}
	151
	152	static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
	153	{
	154	phys_addr_t jumpaddr;
	155	unsigned int remap_reg_value = 0;
	156	struct device_node *node;
	157
	158
64fc2a94	159	jumpaddr = __pa_symbol(secondary_startup);
7fda91e7 WL	160	hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
	161
	162	node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
	163	if (WARN_ON(!node))
	164	return -1;
	165	ctrl_base = of_iomap(node, 0);
9bc72e47	166	of_node_put(node);
7fda91e7 WL	167
	168	/* set the secondary core boot from DDR */
	169	remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL);
	170	barrier();
	171	remap_reg_value \|= SC_SCTL_REMAP_CLR;
	172	barrier();
	173	writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL);
	174
	175	hip01_set_cpu(cpu, true);
	176
	177	return 0;
	178	}
	179
75305275	180	static const struct smp_operations hip01_smp_ops __initconst = {
7fda91e7 WL	181	.smp_prepare_cpus = hisi_common_smp_prepare_cpus,
	182	.smp_boot_secondary = hip01_boot_secondary,
	183	};
	184
c2fff85e HZ	185	CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3620-smp", &hi3xxx_smp_ops);
c2fff85e HZ	186	CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);
7fda91e7	187	CPU_METHOD_OF_DECLARE(hip01_smp, "hisilicon,hip01-smp", &hip01_smp_ops);