[linux-block.git] / arch / arm / mach-h720x / common.c

/*
 * linux/arch/arm/mach-h720x/common.c
 *
 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
 *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
 *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
 *
 * common stuff for Hynix h720x processors
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/sched.h>
#include <linux/mman.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/dma.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <mach/irqs.h>

#include <asm/mach/dma.h>

#if 0
#define IRQDBG(args...) printk(args)
#else
#define IRQDBG(args...) do {} while(0)
#endif

void __init arch_dma_init(dma_t *dma)
{
}

/*
 * Return usecs since last timer reload
 * (timercount * (usecs perjiffie)) / (ticks per jiffie)
 */
unsigned long h720x_gettimeoffset(void)
{
	return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
}

/*
 * mask Global irq's
 */
static void mask_global_irq (unsigned int irq )
{
	CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq);
}

/*
 * unmask Global irq's
 */
static void unmask_global_irq (unsigned int irq )
{
	CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq);
}


/*
 * ack GPIO irq's
 * Ack only for edge triggered int's valid
 */
static void inline ack_gpio_irq(u32 irq)
{
	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
	u32 bit = IRQ_TO_BIT(irq);
	if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
		CPU_REG (reg_base, GPIO_CLR) = bit;
}

/*
 * mask GPIO irq's
 */
static void inline mask_gpio_irq(u32 irq)
{
	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
	u32 bit = IRQ_TO_BIT(irq);
	CPU_REG (reg_base, GPIO_MASK) &= ~bit;
}

/*
 * unmask GPIO irq's
 */
static void inline unmask_gpio_irq(u32 irq)
{
	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
	u32 bit = IRQ_TO_BIT(irq);
	CPU_REG (reg_base, GPIO_MASK) |= bit;
}

static void
h720x_gpio_handler(unsigned int mask, unsigned int irq,
                 struct irq_desc *desc)
{
	IRQDBG("%s irq: %d\n", __func__, irq);
	while (mask) {
		if (mask & 1) {
			IRQDBG("handling irq %d\n", irq);
			generic_handle_irq(irq);
		}
		irq++;
		mask >>= 1;
	}
}

static void
h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
	irq = IRQ_CHAINED_GPIOA(0);
	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
	h720x_gpio_handler(mask, irq, desc);
}

static void
h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;
	mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
	irq = IRQ_CHAINED_GPIOB(0);
	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
	h720x_gpio_handler(mask, irq, desc);
}

static void
h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
	irq = IRQ_CHAINED_GPIOC(0);
	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
	h720x_gpio_handler(mask, irq, desc);
}

static void
h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
	irq = IRQ_CHAINED_GPIOD(0);
	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
	h720x_gpio_handler(mask, irq, desc);
}

#ifdef CONFIG_CPU_H7202
static void
h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
	irq = IRQ_CHAINED_GPIOE(0);
	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
	h720x_gpio_handler(mask, irq, desc);
}
#endif

static struct irq_chip h720x_global_chip = {
	.ack = mask_global_irq,
	.mask = mask_global_irq,
	.unmask = unmask_global_irq,
};

static struct irq_chip h720x_gpio_chip = {
	.ack = ack_gpio_irq,
	.mask = mask_gpio_irq,
	.unmask = unmask_gpio_irq,
};

/*
 * Initialize IRQ's, mask all, enable multiplexed irq's
 */
void __init h720x_init_irq (void)
{
	int 	irq;

	/* Mask global irq's */
	CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;

	/* Mask all multiplexed irq's */
	CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
	CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
	CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
	CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;

	/* Initialize global IRQ's, fast path */
	for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
		set_irq_chip(irq, &h720x_global_chip);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	/* Initialize multiplexed IRQ's, slow path */
	for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
		set_irq_chip(irq, &h720x_gpio_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID );
	}
	set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
	set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
	set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
	set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);

#ifdef CONFIG_CPU_H7202
	for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
		set_irq_chip(irq, &h720x_gpio_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID );
	}
	set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
#endif

	/* Enable multiplexed irq's */
	CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
}

static struct map_desc h720x_io_desc[] __initdata = {
	{
		.virtual	= IO_VIRT,
		.pfn		= __phys_to_pfn(IO_PHYS),
		.length		= IO_SIZE,
		.type		= MT_DEVICE
	},
};

/* Initialize io tables */
void __init h720x_map_io(void)
{
	iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-h720x/common.c
	3	*
	4	* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
	5	* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
	6	* 2004 Sascha Hauer <s.hauer@pengutronix.de>
	7	*
	8	* common stuff for Hynix h720x processors
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	*/
	15
	16	#include <linux/sched.h>
1da177e4 LT	17	#include <linux/mman.h>
	18	#include <linux/init.h>
	19	#include <linux/interrupt.h>
fced80c7	20	#include <linux/io.h>
1da177e4 LT	21
	22	#include <asm/page.h>
	23	#include <asm/pgtable.h>
	24	#include <asm/dma.h>
a09e64fb	25	#include <mach/hardware.h>
1da177e4 LT	26	#include <asm/irq.h>
	27	#include <asm/mach/irq.h>
	28	#include <asm/mach/map.h>
a09e64fb	29	#include <mach/irqs.h>
1da177e4 LT	30
	31	#include <asm/mach/dma.h>
	32
	33	#if 0
	34	#define IRQDBG(args...) printk(args)
	35	#else
	36	#define IRQDBG(args...) do {} while(0)
	37	#endif
	38
	39	void __init arch_dma_init(dma_t *dma)
	40	{
	41	}
	42
	43	/*
	44	* Return usecs since last timer reload
	45	* (timercount * (usecs perjiffie)) / (ticks per jiffie)
	46	*/
	47	unsigned long h720x_gettimeoffset(void)
	48	{
	49	return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
	50	}
	51
	52	/*
	53	* mask Global irq's
	54	*/
	55	static void mask_global_irq (unsigned int irq )
	56	{
	57	CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq);
	58	}
	59
	60	/*
	61	* unmask Global irq's
	62	*/
	63	static void unmask_global_irq (unsigned int irq )
	64	{
	65	CPU_REG (IRQC_VIRT, IRQC_IER) \|= (1 << irq);
	66	}
	67
	68
	69	/*
	70	* ack GPIO irq's
	71	* Ack only for edge triggered int's valid
	72	*/
	73	static void inline ack_gpio_irq(u32 irq)
	74	{
	75	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
	76	u32 bit = IRQ_TO_BIT(irq);
	77	if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
	78	CPU_REG (reg_base, GPIO_CLR) = bit;
	79	}
	80
	81	/*
	82	* mask GPIO irq's
	83	*/
	84	static void inline mask_gpio_irq(u32 irq)
	85	{
	86	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
	87	u32 bit = IRQ_TO_BIT(irq);
	88	CPU_REG (reg_base, GPIO_MASK) &= ~bit;
	89	}
	90
	91	/*
	92	* unmask GPIO irq's
	93	*/
94	static void inline unmask_gpio_irq(u32 irq)
95	{
96	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
97	u32 bit = IRQ_TO_BIT(irq);
98	CPU_REG (reg_base, GPIO_MASK) \|= bit;
99	}
100
101	static void
102	h720x_gpio_handler(unsigned int mask, unsigned int irq,
10dd5ce2	103	struct irq_desc *desc)
1da177e4	104	{
8e86f427	105	IRQDBG("%s irq: %d\n", __func__, irq);
1da177e4 LT	106	while (mask) {
	107	if (mask & 1) {
	108	IRQDBG("handling irq %d\n", irq);
d8aa0251	109	generic_handle_irq(irq);
1da177e4 LT	110	}
1da177e4 LT	111	irq++;
1da177e4 LT	112	mask >>= 1;
	113	}
	114	}
	115
	116	static void
10dd5ce2	117	h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	118	{
	119	unsigned int mask, irq;
	120
	121	mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
	122	irq = IRQ_CHAINED_GPIOA(0);
8e86f427	123	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
0cd61b68	124	h720x_gpio_handler(mask, irq, desc);
1da177e4 LT	125	}
	126
	127	static void
10dd5ce2	128	h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	129	{
	130	unsigned int mask, irq;
	131	mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
	132	irq = IRQ_CHAINED_GPIOB(0);
8e86f427	133	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
0cd61b68	134	h720x_gpio_handler(mask, irq, desc);
1da177e4 LT	135	}
	136
	137	static void
10dd5ce2	138	h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	139	{
	140	unsigned int mask, irq;
	141
	142	mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
	143	irq = IRQ_CHAINED_GPIOC(0);
8e86f427	144	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
0cd61b68	145	h720x_gpio_handler(mask, irq, desc);
1da177e4 LT	146	}
	147
	148	static void
10dd5ce2	149	h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	150	{
	151	unsigned int mask, irq;
	152
	153	mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
	154	irq = IRQ_CHAINED_GPIOD(0);
8e86f427	155	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
0cd61b68	156	h720x_gpio_handler(mask, irq, desc);
1da177e4 LT	157	}
	158
	159	#ifdef CONFIG_CPU_H7202
	160	static void
10dd5ce2	161	h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	162	{
	163	unsigned int mask, irq;
	164
	165	mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
	166	irq = IRQ_CHAINED_GPIOE(0);
8e86f427	167	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
0cd61b68	168	h720x_gpio_handler(mask, irq, desc);
1da177e4 LT	169	}
	170	#endif
	171
10dd5ce2	172	static struct irq_chip h720x_global_chip = {
1da177e4 LT	173	.ack = mask_global_irq,
	174	.mask = mask_global_irq,
	175	.unmask = unmask_global_irq,
	176	};
	177
10dd5ce2	178	static struct irq_chip h720x_gpio_chip = {
1da177e4 LT	179	.ack = ack_gpio_irq,
	180	.mask = mask_gpio_irq,
	181	.unmask = unmask_gpio_irq,
	182	};
	183
	184	/*
	185	* Initialize IRQ's, mask all, enable multiplexed irq's
	186	*/
	187	void __init h720x_init_irq (void)
	188	{
	189	int irq;
	190
	191	/* Mask global irq's */
	192	CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
	193
	194	/* Mask all multiplexed irq's */
	195	CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
	196	CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
	197	CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
	198	CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
	199
	200	/* Initialize global IRQ's, fast path */
	201	for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
	202	set_irq_chip(irq, &h720x_global_chip);
10dd5ce2	203	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	204	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	205	}
	206
	207	/* Initialize multiplexed IRQ's, slow path */
	208	for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
	209	set_irq_chip(irq, &h720x_gpio_chip);
10dd5ce2	210	set_irq_handler(irq, handle_edge_irq);
1da177e4 LT	211	set_irq_flags(irq, IRQF_VALID );
	212	}
	213	set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
	214	set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
	215	set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
	216	set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
	217
	218	#ifdef CONFIG_CPU_H7202
	219	for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
	220	set_irq_chip(irq, &h720x_gpio_chip);
10dd5ce2	221	set_irq_handler(irq, handle_edge_irq);
1da177e4 LT	222	set_irq_flags(irq, IRQF_VALID );
	223	}
	224	set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
	225	#endif
	226
	227	/* Enable multiplexed irq's */
	228	CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
	229	}
	230
	231	static struct map_desc h720x_io_desc[] __initdata = {
3e9635e4 DS	232	{
	233	.virtual = IO_VIRT,
	234	.pfn = __phys_to_pfn(IO_PHYS),
	235	.length = IO_SIZE,
	236	.type = MT_DEVICE
	237	},
1da177e4 LT	238	};
	239
	240	/* Initialize io tables */
	241	void __init h720x_map_io(void)
	242	{
	243	iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
	244	}