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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * linux/arch/arm/mach-footbridge/common.c | |
4 | * | |
5 | * Copyright (C) 1998-2000 Russell King, Dave Gilbert. | |
1da177e4 | 6 | */ |
1da177e4 LT |
7 | #include <linux/module.h> |
8 | #include <linux/types.h> | |
9 | #include <linux/mm.h> | |
10 | #include <linux/ioport.h> | |
11 | #include <linux/list.h> | |
12 | #include <linux/init.h> | |
fced80c7 | 13 | #include <linux/io.h> |
70d13e08 | 14 | #include <linux/spinlock.h> |
af6f23b8 | 15 | #include <linux/dma-direct.h> |
43659222 | 16 | #include <video/vga.h> |
8ef6e620 | 17 | |
1da177e4 LT |
18 | #include <asm/page.h> |
19 | #include <asm/irq.h> | |
1da177e4 LT |
20 | #include <asm/mach-types.h> |
21 | #include <asm/setup.h> | |
9f97da78 | 22 | #include <asm/system_misc.h> |
1da177e4 LT |
23 | #include <asm/hardware/dec21285.h> |
24 | ||
25 | #include <asm/mach/irq.h> | |
26 | #include <asm/mach/map.h> | |
8ef6e620 | 27 | #include <asm/mach/pci.h> |
1da177e4 LT |
28 | |
29 | #include "common.h" | |
30 | ||
90890f17 AB |
31 | #include <mach/hardware.h> |
32 | #include <mach/irqs.h> | |
33 | #include <asm/hardware/dec21285.h> | |
34 | ||
35 | static int dc21285_get_irq(void) | |
36 | { | |
37 | void __iomem *irqstatus = (void __iomem *)CSR_IRQ_STATUS; | |
38 | u32 mask = readl(irqstatus); | |
39 | ||
40 | if (mask & IRQ_MASK_SDRAMPARITY) | |
41 | return IRQ_SDRAMPARITY; | |
42 | ||
43 | if (mask & IRQ_MASK_UART_RX) | |
44 | return IRQ_CONRX; | |
45 | ||
46 | if (mask & IRQ_MASK_DMA1) | |
47 | return IRQ_DMA1; | |
48 | ||
49 | if (mask & IRQ_MASK_DMA2) | |
50 | return IRQ_DMA2; | |
51 | ||
52 | if (mask & IRQ_MASK_IN0) | |
53 | return IRQ_IN0; | |
54 | ||
55 | if (mask & IRQ_MASK_IN1) | |
56 | return IRQ_IN1; | |
57 | ||
58 | if (mask & IRQ_MASK_IN2) | |
59 | return IRQ_IN2; | |
60 | ||
61 | if (mask & IRQ_MASK_IN3) | |
62 | return IRQ_IN3; | |
63 | ||
64 | if (mask & IRQ_MASK_PCI) | |
65 | return IRQ_PCI; | |
66 | ||
67 | if (mask & IRQ_MASK_DOORBELLHOST) | |
68 | return IRQ_DOORBELLHOST; | |
69 | ||
70 | if (mask & IRQ_MASK_I2OINPOST) | |
71 | return IRQ_I2OINPOST; | |
72 | ||
73 | if (mask & IRQ_MASK_TIMER1) | |
74 | return IRQ_TIMER1; | |
75 | ||
76 | if (mask & IRQ_MASK_TIMER2) | |
77 | return IRQ_TIMER2; | |
78 | ||
79 | if (mask & IRQ_MASK_TIMER3) | |
80 | return IRQ_TIMER3; | |
81 | ||
82 | if (mask & IRQ_MASK_UART_TX) | |
83 | return IRQ_CONTX; | |
84 | ||
85 | if (mask & IRQ_MASK_PCI_ABORT) | |
86 | return IRQ_PCI_ABORT; | |
87 | ||
88 | if (mask & IRQ_MASK_PCI_SERR) | |
89 | return IRQ_PCI_SERR; | |
90 | ||
91 | if (mask & IRQ_MASK_DISCARD_TIMER) | |
92 | return IRQ_DISCARD_TIMER; | |
93 | ||
94 | if (mask & IRQ_MASK_PCI_DPERR) | |
95 | return IRQ_PCI_DPERR; | |
96 | ||
97 | if (mask & IRQ_MASK_PCI_PERR) | |
98 | return IRQ_PCI_PERR; | |
99 | ||
100 | return 0; | |
101 | } | |
102 | ||
103 | static void dc21285_handle_irq(struct pt_regs *regs) | |
104 | { | |
105 | int irq; | |
106 | do { | |
107 | irq = dc21285_get_irq(); | |
108 | if (!irq) | |
109 | break; | |
110 | ||
111 | generic_handle_irq(irq); | |
112 | } while (1); | |
113 | } | |
114 | ||
115 | ||
1da177e4 LT |
116 | unsigned int mem_fclk_21285 = 50000000; |
117 | ||
118 | EXPORT_SYMBOL(mem_fclk_21285); | |
119 | ||
2b0d8c25 | 120 | static int __init early_fclk(char *arg) |
613e09b4 | 121 | { |
2b0d8c25 JK |
122 | mem_fclk_21285 = simple_strtoul(arg, NULL, 0); |
123 | return 0; | |
613e09b4 RK |
124 | } |
125 | ||
2b0d8c25 | 126 | early_param("mem_fclk_21285", early_fclk); |
613e09b4 | 127 | |
1da177e4 LT |
128 | static int __init parse_tag_memclk(const struct tag *tag) |
129 | { | |
130 | mem_fclk_21285 = tag->u.memclk.fmemclk; | |
131 | return 0; | |
132 | } | |
133 | ||
134 | __tagtable(ATAG_MEMCLK, parse_tag_memclk); | |
135 | ||
136 | /* | |
137 | * Footbridge IRQ translation table | |
138 | * Converts from our IRQ numbers into FootBridge masks | |
139 | */ | |
140 | static const int fb_irq_mask[] = { | |
141 | IRQ_MASK_UART_RX, /* 0 */ | |
142 | IRQ_MASK_UART_TX, /* 1 */ | |
143 | IRQ_MASK_TIMER1, /* 2 */ | |
144 | IRQ_MASK_TIMER2, /* 3 */ | |
145 | IRQ_MASK_TIMER3, /* 4 */ | |
146 | IRQ_MASK_IN0, /* 5 */ | |
147 | IRQ_MASK_IN1, /* 6 */ | |
148 | IRQ_MASK_IN2, /* 7 */ | |
149 | IRQ_MASK_IN3, /* 8 */ | |
150 | IRQ_MASK_DOORBELLHOST, /* 9 */ | |
151 | IRQ_MASK_DMA1, /* 10 */ | |
152 | IRQ_MASK_DMA2, /* 11 */ | |
153 | IRQ_MASK_PCI, /* 12 */ | |
154 | IRQ_MASK_SDRAMPARITY, /* 13 */ | |
155 | IRQ_MASK_I2OINPOST, /* 14 */ | |
156 | IRQ_MASK_PCI_ABORT, /* 15 */ | |
157 | IRQ_MASK_PCI_SERR, /* 16 */ | |
158 | IRQ_MASK_DISCARD_TIMER, /* 17 */ | |
159 | IRQ_MASK_PCI_DPERR, /* 18 */ | |
160 | IRQ_MASK_PCI_PERR, /* 19 */ | |
161 | }; | |
162 | ||
dc2caf6c | 163 | static void fb_mask_irq(struct irq_data *d) |
1da177e4 | 164 | { |
dc2caf6c | 165 | *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)]; |
1da177e4 LT |
166 | } |
167 | ||
dc2caf6c | 168 | static void fb_unmask_irq(struct irq_data *d) |
1da177e4 | 169 | { |
dc2caf6c | 170 | *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)]; |
1da177e4 LT |
171 | } |
172 | ||
10dd5ce2 | 173 | static struct irq_chip fb_chip = { |
dc2caf6c LB |
174 | .irq_ack = fb_mask_irq, |
175 | .irq_mask = fb_mask_irq, | |
176 | .irq_unmask = fb_unmask_irq, | |
1da177e4 LT |
177 | }; |
178 | ||
179 | static void __init __fb_init_irq(void) | |
180 | { | |
181 | unsigned int irq; | |
182 | ||
183 | /* | |
184 | * setup DC21285 IRQs | |
185 | */ | |
186 | *CSR_IRQ_DISABLE = -1; | |
187 | *CSR_FIQ_DISABLE = -1; | |
188 | ||
189 | for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { | |
f38c02f3 | 190 | irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq); |
e8d36d5d | 191 | irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
1da177e4 LT |
192 | } |
193 | } | |
194 | ||
195 | void __init footbridge_init_irq(void) | |
196 | { | |
90890f17 AB |
197 | set_handle_irq(dc21285_handle_irq); |
198 | ||
1da177e4 LT |
199 | __fb_init_irq(); |
200 | ||
201 | if (!footbridge_cfn_mode()) | |
202 | return; | |
203 | ||
204 | if (machine_is_ebsa285()) | |
205 | /* The following is dependent on which slot | |
206 | * you plug the Southbridge card into. We | |
207 | * currently assume that you plug it into | |
208 | * the right-hand most slot. | |
209 | */ | |
210 | isa_init_irq(IRQ_PCI); | |
211 | ||
212 | if (machine_is_cats()) | |
213 | isa_init_irq(IRQ_IN2); | |
214 | ||
215 | if (machine_is_netwinder()) | |
216 | isa_init_irq(IRQ_IN3); | |
217 | } | |
218 | ||
219 | /* | |
220 | * Common mapping for all systems. Note that the outbound write flush is | |
221 | * commented out since there is a "No Fix" problem with it. Not mapping | |
222 | * it means that we have extra bullet protection on our feet. | |
223 | */ | |
224 | static struct map_desc fb_common_io_desc[] __initdata = { | |
a427ceef DS |
225 | { |
226 | .virtual = ARMCSR_BASE, | |
865052fd | 227 | .pfn = __phys_to_pfn(DC21285_ARMCSR_BASE), |
a427ceef | 228 | .length = ARMCSR_SIZE, |
6460177f | 229 | .type = MT_DEVICE, |
a427ceef | 230 | } |
1da177e4 LT |
231 | }; |
232 | ||
233 | /* | |
234 | * The mapping when the footbridge is in host mode. We don't map any of | |
235 | * this when we are in add-in mode. | |
236 | */ | |
237 | static struct map_desc ebsa285_host_io_desc[] __initdata = { | |
238 | #if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST) | |
a427ceef DS |
239 | { |
240 | .virtual = PCIMEM_BASE, | |
241 | .pfn = __phys_to_pfn(DC21285_PCI_MEM), | |
242 | .length = PCIMEM_SIZE, | |
6460177f | 243 | .type = MT_DEVICE, |
a427ceef DS |
244 | }, { |
245 | .virtual = PCICFG0_BASE, | |
246 | .pfn = __phys_to_pfn(DC21285_PCI_TYPE_0_CONFIG), | |
247 | .length = PCICFG0_SIZE, | |
6460177f | 248 | .type = MT_DEVICE, |
a427ceef DS |
249 | }, { |
250 | .virtual = PCICFG1_BASE, | |
251 | .pfn = __phys_to_pfn(DC21285_PCI_TYPE_1_CONFIG), | |
252 | .length = PCICFG1_SIZE, | |
6460177f | 253 | .type = MT_DEVICE, |
a427ceef DS |
254 | }, { |
255 | .virtual = PCIIACK_BASE, | |
256 | .pfn = __phys_to_pfn(DC21285_PCI_IACK), | |
257 | .length = PCIIACK_SIZE, | |
6460177f | 258 | .type = MT_DEVICE, |
6460177f | 259 | }, |
1da177e4 LT |
260 | #endif |
261 | }; | |
262 | ||
1da177e4 LT |
263 | void __init footbridge_map_io(void) |
264 | { | |
265 | /* | |
266 | * Set up the common mapping first; we need this to | |
267 | * determine whether we're in host mode or not. | |
268 | */ | |
269 | iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc)); | |
270 | ||
271 | /* | |
272 | * Now, work out what we've got to map in addition on this | |
273 | * platform. | |
274 | */ | |
8ef6e620 | 275 | if (footbridge_cfn_mode()) { |
1da177e4 | 276 | iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc)); |
8ef6e620 RH |
277 | pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO)); |
278 | } | |
43659222 RK |
279 | |
280 | vga_base = PCIMEM_BASE; | |
1da177e4 LT |
281 | } |
282 | ||
7b6d864b | 283 | void footbridge_restart(enum reboot_mode mode, const char *cmd) |
6fca1e17 | 284 | { |
7b6d864b | 285 | if (mode == REBOOT_SOFT) { |
6fca1e17 RK |
286 | /* Jump into the ROM */ |
287 | soft_restart(0x41000000); | |
288 | } else { | |
289 | /* | |
290 | * Force the watchdog to do a CPU reset. | |
291 | * | |
292 | * After making sure that the watchdog is disabled | |
293 | * (so we can change the timer registers) we first | |
294 | * enable the timer to autoreload itself. Next, the | |
295 | * timer interval is set really short and any | |
296 | * current interrupt request is cleared (so we can | |
297 | * see an edge transition). Finally, TIMER4 is | |
298 | * enabled as the watchdog. | |
299 | */ | |
300 | *CSR_SA110_CNTL &= ~(1 << 13); | |
301 | *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE | | |
302 | TIMER_CNTL_AUTORELOAD | | |
303 | TIMER_CNTL_DIV16; | |
304 | *CSR_TIMER4_LOAD = 0x2; | |
305 | *CSR_TIMER4_CLR = 0; | |
306 | *CSR_SA110_CNTL |= (1 << 13); | |
307 | } | |
308 | } | |
309 | ||
1da177e4 LT |
310 | #ifdef CONFIG_FOOTBRIDGE_ADDIN |
311 | ||
c7baab5d RK |
312 | static inline unsigned long fb_bus_sdram_offset(void) |
313 | { | |
314 | return *CSR_PCISDRAMBASE & 0xfffffff0; | |
315 | } | |
316 | ||
1da177e4 LT |
317 | /* |
318 | * These two functions convert virtual addresses to PCI addresses and PCI | |
319 | * addresses to virtual addresses. Note that it is only legal to use these | |
320 | * on memory obtained via get_zeroed_page or kmalloc. | |
321 | */ | |
322 | unsigned long __virt_to_bus(unsigned long res) | |
323 | { | |
324 | WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory); | |
325 | ||
c7baab5d | 326 | return res + (fb_bus_sdram_offset() - PAGE_OFFSET); |
1da177e4 LT |
327 | } |
328 | EXPORT_SYMBOL(__virt_to_bus); | |
329 | ||
330 | unsigned long __bus_to_virt(unsigned long res) | |
331 | { | |
c7baab5d | 332 | res = res - (fb_bus_sdram_offset() - PAGE_OFFSET); |
1da177e4 LT |
333 | |
334 | WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory); | |
335 | ||
336 | return res; | |
337 | } | |
338 | EXPORT_SYMBOL(__bus_to_virt); | |
af6f23b8 CH |
339 | #else |
340 | static inline unsigned long fb_bus_sdram_offset(void) | |
c7baab5d | 341 | { |
af6f23b8 | 342 | return BUS_OFFSET; |
c7baab5d | 343 | } |
af6f23b8 | 344 | #endif /* CONFIG_FOOTBRIDGE_ADDIN */ |
c7baab5d | 345 | |
af6f23b8 | 346 | dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) |
c7baab5d | 347 | { |
af6f23b8 | 348 | return paddr + (fb_bus_sdram_offset() - PHYS_OFFSET); |
c7baab5d | 349 | } |
c7baab5d | 350 | |
af6f23b8 CH |
351 | phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr) |
352 | { | |
353 | return dev_addr - (fb_bus_sdram_offset() - PHYS_OFFSET); | |
354 | } |