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1663895c JL |
1 | /* linux/arch/arm/mach-exynos4/pm.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * EXYNOS4210 - Power Management support | |
7 | * | |
8 | * Based on arch/arm/mach-s3c2410/pm.c | |
9 | * Copyright (c) 2006 Simtec Electronics | |
10 | * Ben Dooks <ben@simtec.co.uk> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/suspend.h> | |
bb072c3c | 19 | #include <linux/syscore_ops.h> |
1663895c | 20 | #include <linux/io.h> |
56c03d91 JL |
21 | #include <linux/err.h> |
22 | #include <linux/clk.h> | |
1663895c JL |
23 | |
24 | #include <asm/cacheflush.h> | |
25 | #include <asm/hardware/cache-l2x0.h> | |
26 | ||
27 | #include <plat/cpu.h> | |
28 | #include <plat/pm.h> | |
56c03d91 | 29 | #include <plat/pll.h> |
b93cb91b | 30 | #include <plat/regs-srom.h> |
1663895c JL |
31 | |
32 | #include <mach/regs-irq.h> | |
33 | #include <mach/regs-gpio.h> | |
34 | #include <mach/regs-clock.h> | |
35 | #include <mach/regs-pmu.h> | |
36 | #include <mach/pm-core.h> | |
e4cf2d14 | 37 | #include <mach/pmu.h> |
1663895c JL |
38 | |
39 | static struct sleep_save exynos4_set_clksrc[] = { | |
40 | { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, | |
41 | { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, }, | |
42 | { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, }, | |
43 | { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, | |
44 | { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, | |
45 | { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, | |
46 | { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, }, | |
47 | { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, | |
48 | { .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, | |
49 | { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, | |
50 | }; | |
51 | ||
56c03d91 JL |
52 | static struct sleep_save exynos4_epll_save[] = { |
53 | SAVE_ITEM(S5P_EPLL_CON0), | |
54 | SAVE_ITEM(S5P_EPLL_CON1), | |
55 | }; | |
56 | ||
57 | static struct sleep_save exynos4_vpll_save[] = { | |
58 | SAVE_ITEM(S5P_VPLL_CON0), | |
59 | SAVE_ITEM(S5P_VPLL_CON1), | |
60 | }; | |
61 | ||
1663895c JL |
62 | static struct sleep_save exynos4_core_save[] = { |
63 | /* CMU side */ | |
64 | SAVE_ITEM(S5P_CLKDIV_LEFTBUS), | |
65 | SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), | |
66 | SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), | |
67 | SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), | |
1663895c JL |
68 | SAVE_ITEM(S5P_CLKSRC_TOP0), |
69 | SAVE_ITEM(S5P_CLKSRC_TOP1), | |
70 | SAVE_ITEM(S5P_CLKSRC_CAM), | |
b93cb91b | 71 | SAVE_ITEM(S5P_CLKSRC_TV), |
1663895c | 72 | SAVE_ITEM(S5P_CLKSRC_MFC), |
b93cb91b | 73 | SAVE_ITEM(S5P_CLKSRC_G3D), |
1663895c JL |
74 | SAVE_ITEM(S5P_CLKSRC_IMAGE), |
75 | SAVE_ITEM(S5P_CLKSRC_LCD0), | |
76 | SAVE_ITEM(S5P_CLKSRC_LCD1), | |
77 | SAVE_ITEM(S5P_CLKSRC_MAUDIO), | |
78 | SAVE_ITEM(S5P_CLKSRC_FSYS), | |
79 | SAVE_ITEM(S5P_CLKSRC_PERIL0), | |
80 | SAVE_ITEM(S5P_CLKSRC_PERIL1), | |
81 | SAVE_ITEM(S5P_CLKDIV_CAM), | |
82 | SAVE_ITEM(S5P_CLKDIV_TV), | |
83 | SAVE_ITEM(S5P_CLKDIV_MFC), | |
84 | SAVE_ITEM(S5P_CLKDIV_G3D), | |
85 | SAVE_ITEM(S5P_CLKDIV_IMAGE), | |
86 | SAVE_ITEM(S5P_CLKDIV_LCD0), | |
87 | SAVE_ITEM(S5P_CLKDIV_LCD1), | |
88 | SAVE_ITEM(S5P_CLKDIV_MAUDIO), | |
89 | SAVE_ITEM(S5P_CLKDIV_FSYS0), | |
90 | SAVE_ITEM(S5P_CLKDIV_FSYS1), | |
91 | SAVE_ITEM(S5P_CLKDIV_FSYS2), | |
92 | SAVE_ITEM(S5P_CLKDIV_FSYS3), | |
93 | SAVE_ITEM(S5P_CLKDIV_PERIL0), | |
94 | SAVE_ITEM(S5P_CLKDIV_PERIL1), | |
95 | SAVE_ITEM(S5P_CLKDIV_PERIL2), | |
96 | SAVE_ITEM(S5P_CLKDIV_PERIL3), | |
97 | SAVE_ITEM(S5P_CLKDIV_PERIL4), | |
98 | SAVE_ITEM(S5P_CLKDIV_PERIL5), | |
99 | SAVE_ITEM(S5P_CLKDIV_TOP), | |
b93cb91b | 100 | SAVE_ITEM(S5P_CLKSRC_MASK_TOP), |
1663895c JL |
101 | SAVE_ITEM(S5P_CLKSRC_MASK_CAM), |
102 | SAVE_ITEM(S5P_CLKSRC_MASK_TV), | |
103 | SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), | |
104 | SAVE_ITEM(S5P_CLKSRC_MASK_LCD1), | |
105 | SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO), | |
106 | SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), | |
107 | SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), | |
108 | SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), | |
b93cb91b | 109 | SAVE_ITEM(S5P_CLKDIV2_RATIO), |
1663895c JL |
110 | SAVE_ITEM(S5P_CLKGATE_SCLKCAM), |
111 | SAVE_ITEM(S5P_CLKGATE_IP_CAM), | |
112 | SAVE_ITEM(S5P_CLKGATE_IP_TV), | |
113 | SAVE_ITEM(S5P_CLKGATE_IP_MFC), | |
114 | SAVE_ITEM(S5P_CLKGATE_IP_G3D), | |
115 | SAVE_ITEM(S5P_CLKGATE_IP_IMAGE), | |
116 | SAVE_ITEM(S5P_CLKGATE_IP_LCD0), | |
117 | SAVE_ITEM(S5P_CLKGATE_IP_LCD1), | |
118 | SAVE_ITEM(S5P_CLKGATE_IP_FSYS), | |
119 | SAVE_ITEM(S5P_CLKGATE_IP_GPS), | |
120 | SAVE_ITEM(S5P_CLKGATE_IP_PERIL), | |
121 | SAVE_ITEM(S5P_CLKGATE_IP_PERIR), | |
122 | SAVE_ITEM(S5P_CLKGATE_BLOCK), | |
123 | SAVE_ITEM(S5P_CLKSRC_MASK_DMC), | |
124 | SAVE_ITEM(S5P_CLKSRC_DMC), | |
125 | SAVE_ITEM(S5P_CLKDIV_DMC0), | |
126 | SAVE_ITEM(S5P_CLKDIV_DMC1), | |
127 | SAVE_ITEM(S5P_CLKGATE_IP_DMC), | |
128 | SAVE_ITEM(S5P_CLKSRC_CPU), | |
129 | SAVE_ITEM(S5P_CLKDIV_CPU), | |
b93cb91b | 130 | SAVE_ITEM(S5P_CLKDIV_CPU + 0x4), |
1663895c JL |
131 | SAVE_ITEM(S5P_CLKGATE_SCLKCPU), |
132 | SAVE_ITEM(S5P_CLKGATE_IP_CPU), | |
b93cb91b | 133 | |
1663895c JL |
134 | /* GIC side */ |
135 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), | |
136 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), | |
137 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x008), | |
138 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C), | |
139 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x014), | |
140 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x018), | |
141 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x000), | |
142 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x004), | |
143 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x100), | |
144 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x104), | |
145 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x108), | |
146 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x300), | |
147 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x304), | |
148 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x308), | |
149 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x400), | |
150 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x404), | |
151 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x408), | |
152 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C), | |
153 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x410), | |
154 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x414), | |
155 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x418), | |
156 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C), | |
157 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x420), | |
158 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x424), | |
159 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x428), | |
160 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C), | |
161 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x430), | |
162 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x434), | |
163 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x438), | |
164 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C), | |
165 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x440), | |
166 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x444), | |
167 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x448), | |
168 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C), | |
169 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x450), | |
170 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x454), | |
171 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x458), | |
172 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C), | |
173 | ||
174 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x800), | |
175 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x804), | |
176 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x808), | |
177 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C), | |
178 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x810), | |
179 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x814), | |
180 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x818), | |
181 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C), | |
182 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x820), | |
183 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x824), | |
184 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x828), | |
185 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C), | |
186 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x830), | |
187 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x834), | |
188 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x838), | |
189 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C), | |
190 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x840), | |
191 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x844), | |
192 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x848), | |
193 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C), | |
194 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x850), | |
195 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x854), | |
196 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x858), | |
197 | SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C), | |
198 | ||
199 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00), | |
200 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04), | |
201 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08), | |
202 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C), | |
203 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10), | |
204 | SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14), | |
205 | ||
206 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000), | |
207 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010), | |
208 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020), | |
209 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030), | |
210 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040), | |
211 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050), | |
212 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060), | |
213 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), | |
214 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080), | |
215 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090), | |
b93cb91b MH |
216 | |
217 | /* SROM side */ | |
218 | SAVE_ITEM(S5P_SROM_BW), | |
219 | SAVE_ITEM(S5P_SROM_BC0), | |
220 | SAVE_ITEM(S5P_SROM_BC1), | |
221 | SAVE_ITEM(S5P_SROM_BC2), | |
222 | SAVE_ITEM(S5P_SROM_BC3), | |
1663895c JL |
223 | }; |
224 | ||
225 | static struct sleep_save exynos4_l2cc_save[] = { | |
226 | SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), | |
227 | SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), | |
228 | SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), | |
229 | SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), | |
230 | SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), | |
231 | }; | |
232 | ||
f4ba4b01 JL |
233 | /* For Cortex-A9 Diagnostic and Power control register */ |
234 | static unsigned int save_arm_register[2]; | |
235 | ||
29cb3cd2 | 236 | static int exynos4_cpu_suspend(unsigned long arg) |
1663895c | 237 | { |
1663895c JL |
238 | outer_flush_all(); |
239 | ||
240 | /* issue the standby signal into the pm unit. */ | |
241 | cpu_do_idle(); | |
242 | ||
243 | /* we should never get past here */ | |
244 | panic("sleep resumed to originator?"); | |
245 | } | |
246 | ||
247 | static void exynos4_pm_prepare(void) | |
248 | { | |
249 | u32 tmp; | |
250 | ||
251 | s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); | |
252 | s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); | |
56c03d91 JL |
253 | s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); |
254 | s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); | |
1663895c JL |
255 | |
256 | tmp = __raw_readl(S5P_INFORM1); | |
257 | ||
258 | /* Set value of power down register for sleep mode */ | |
259 | ||
e4cf2d14 | 260 | exynos4_sys_powerdown_conf(SYS_SLEEP); |
1663895c JL |
261 | __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); |
262 | ||
263 | /* ensure at least INFORM0 has the resume address */ | |
264 | ||
265 | __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); | |
266 | ||
267 | /* Before enter central sequence mode, clock src register have to set */ | |
268 | ||
269 | s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); | |
270 | ||
271 | } | |
272 | ||
273 | static int exynos4_pm_add(struct sys_device *sysdev) | |
274 | { | |
275 | pm_cpu_prep = exynos4_pm_prepare; | |
276 | pm_cpu_sleep = exynos4_cpu_suspend; | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
281 | /* This function copy from linux/arch/arm/kernel/smp_scu.c */ | |
282 | ||
283 | void exynos4_scu_enable(void __iomem *scu_base) | |
284 | { | |
285 | u32 scu_ctrl; | |
286 | ||
287 | scu_ctrl = __raw_readl(scu_base); | |
288 | /* already enabled? */ | |
289 | if (scu_ctrl & 1) | |
290 | return; | |
291 | ||
292 | scu_ctrl |= 1; | |
293 | __raw_writel(scu_ctrl, scu_base); | |
294 | ||
295 | /* | |
296 | * Ensure that the data accessed by CPU0 before the SCU was | |
297 | * initialised is visible to the other CPUs. | |
298 | */ | |
299 | flush_cache_all(); | |
300 | } | |
301 | ||
56c03d91 JL |
302 | static unsigned long pll_base_rate; |
303 | ||
304 | static void exynos4_restore_pll(void) | |
305 | { | |
306 | unsigned long pll_con, locktime, lockcnt; | |
307 | unsigned long pll_in_rate; | |
308 | unsigned int p_div, epll_wait = 0, vpll_wait = 0; | |
309 | ||
310 | if (pll_base_rate == 0) | |
311 | return; | |
312 | ||
313 | pll_in_rate = pll_base_rate; | |
314 | ||
315 | /* EPLL */ | |
316 | pll_con = exynos4_epll_save[0].val; | |
317 | ||
318 | if (pll_con & (1 << 31)) { | |
319 | pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT); | |
320 | p_div = (pll_con >> PLL46XX_PDIV_SHIFT); | |
321 | ||
322 | pll_in_rate /= 1000000; | |
323 | ||
324 | locktime = (3000 / pll_in_rate) * p_div; | |
325 | lockcnt = locktime * 10000 / (10000 / pll_in_rate); | |
326 | ||
327 | __raw_writel(lockcnt, S5P_EPLL_LOCK); | |
328 | ||
329 | s3c_pm_do_restore_core(exynos4_epll_save, | |
330 | ARRAY_SIZE(exynos4_epll_save)); | |
331 | epll_wait = 1; | |
332 | } | |
333 | ||
334 | pll_in_rate = pll_base_rate; | |
335 | ||
336 | /* VPLL */ | |
337 | pll_con = exynos4_vpll_save[0].val; | |
338 | ||
339 | if (pll_con & (1 << 31)) { | |
340 | pll_in_rate /= 1000000; | |
341 | /* 750us */ | |
342 | locktime = 750; | |
343 | lockcnt = locktime * 10000 / (10000 / pll_in_rate); | |
344 | ||
345 | __raw_writel(lockcnt, S5P_VPLL_LOCK); | |
346 | ||
347 | s3c_pm_do_restore_core(exynos4_vpll_save, | |
348 | ARRAY_SIZE(exynos4_vpll_save)); | |
349 | vpll_wait = 1; | |
350 | } | |
351 | ||
352 | /* Wait PLL locking */ | |
353 | ||
354 | do { | |
355 | if (epll_wait) { | |
356 | pll_con = __raw_readl(S5P_EPLL_CON0); | |
357 | if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT)) | |
358 | epll_wait = 0; | |
359 | } | |
360 | ||
361 | if (vpll_wait) { | |
362 | pll_con = __raw_readl(S5P_VPLL_CON0); | |
363 | if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT)) | |
364 | vpll_wait = 0; | |
365 | } | |
366 | } while (epll_wait || vpll_wait); | |
367 | } | |
368 | ||
bb072c3c RW |
369 | static struct sysdev_driver exynos4_pm_driver = { |
370 | .add = exynos4_pm_add, | |
371 | }; | |
372 | ||
373 | static __init int exynos4_pm_drvinit(void) | |
374 | { | |
56c03d91 | 375 | struct clk *pll_base; |
bb072c3c RW |
376 | unsigned int tmp; |
377 | ||
378 | s3c_pm_init(); | |
379 | ||
380 | /* All wakeup disable */ | |
381 | ||
382 | tmp = __raw_readl(S5P_WAKEUP_MASK); | |
383 | tmp |= ((0xFF << 8) | (0x1F << 1)); | |
384 | __raw_writel(tmp, S5P_WAKEUP_MASK); | |
385 | ||
56c03d91 JL |
386 | pll_base = clk_get(NULL, "xtal"); |
387 | ||
388 | if (!IS_ERR(pll_base)) { | |
389 | pll_base_rate = clk_get_rate(pll_base); | |
390 | clk_put(pll_base); | |
391 | } | |
392 | ||
bb072c3c RW |
393 | return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); |
394 | } | |
395 | arch_initcall(exynos4_pm_drvinit); | |
396 | ||
12974e9f JL |
397 | static int exynos4_pm_suspend(void) |
398 | { | |
399 | unsigned long tmp; | |
400 | ||
401 | /* Setting Central Sequence Register for power down mode */ | |
402 | ||
403 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
404 | tmp &= ~S5P_CENTRAL_LOWPWR_CFG; | |
405 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
406 | ||
f4ba4b01 JL |
407 | /* Save Power control register */ |
408 | asm ("mrc p15, 0, %0, c15, c0, 0" | |
409 | : "=r" (tmp) : : "cc"); | |
410 | save_arm_register[0] = tmp; | |
411 | ||
412 | /* Save Diagnostic register */ | |
413 | asm ("mrc p15, 0, %0, c15, c0, 1" | |
414 | : "=r" (tmp) : : "cc"); | |
415 | save_arm_register[1] = tmp; | |
416 | ||
12974e9f JL |
417 | return 0; |
418 | } | |
419 | ||
bb072c3c | 420 | static void exynos4_pm_resume(void) |
1663895c | 421 | { |
e240ab1c JL |
422 | unsigned long tmp; |
423 | ||
424 | /* | |
425 | * If PMU failed while entering sleep mode, WFI will be | |
426 | * ignored by PMU and then exiting cpu_do_idle(). | |
427 | * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically | |
428 | * in this situation. | |
429 | */ | |
430 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
431 | if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { | |
432 | tmp |= S5P_CENTRAL_LOWPWR_CFG; | |
433 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
434 | /* No need to perform below restore code */ | |
435 | goto early_wakeup; | |
436 | } | |
f4ba4b01 JL |
437 | /* Restore Power control register */ |
438 | tmp = save_arm_register[0]; | |
439 | asm volatile ("mcr p15, 0, %0, c15, c0, 0" | |
440 | : : "r" (tmp) | |
441 | : "cc"); | |
442 | ||
443 | /* Restore Diagnostic register */ | |
444 | tmp = save_arm_register[1]; | |
445 | asm volatile ("mcr p15, 0, %0, c15, c0, 1" | |
446 | : : "r" (tmp) | |
447 | : "cc"); | |
e240ab1c | 448 | |
1663895c JL |
449 | /* For release retention */ |
450 | ||
451 | __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); | |
452 | __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); | |
453 | __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); | |
454 | __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); | |
455 | __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); | |
456 | __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); | |
457 | __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); | |
458 | ||
459 | s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); | |
460 | ||
56c03d91 JL |
461 | exynos4_restore_pll(); |
462 | ||
1663895c JL |
463 | exynos4_scu_enable(S5P_VA_SCU); |
464 | ||
465 | #ifdef CONFIG_CACHE_L2X0 | |
466 | s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); | |
467 | outer_inv_all(); | |
468 | /* enable L2X0*/ | |
469 | writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); | |
470 | #endif | |
e240ab1c JL |
471 | |
472 | early_wakeup: | |
473 | return; | |
1663895c JL |
474 | } |
475 | ||
bb072c3c | 476 | static struct syscore_ops exynos4_pm_syscore_ops = { |
12974e9f | 477 | .suspend = exynos4_pm_suspend, |
1663895c JL |
478 | .resume = exynos4_pm_resume, |
479 | }; | |
480 | ||
bb072c3c | 481 | static __init int exynos4_pm_syscore_init(void) |
1663895c | 482 | { |
bb072c3c RW |
483 | register_syscore_ops(&exynos4_pm_syscore_ops); |
484 | return 0; | |
1663895c | 485 | } |
bb072c3c | 486 | arch_initcall(exynos4_pm_syscore_init); |