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7d30e8b3 | 1 | /* linux/arch/arm/mach-exynos4/platsmp.c |
2b12b5c4 | 2 | * |
7d30e8b3 KK |
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
2b12b5c4 CY |
5 | * |
6 | * Cloned from linux/arch/arm/mach-vexpress/platsmp.c | |
7 | * | |
8 | * Copyright (C) 2002 ARM Ltd. | |
9 | * All Rights Reserved | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/jiffies.h> | |
21 | #include <linux/smp.h> | |
22 | #include <linux/io.h> | |
23 | ||
24 | #include <asm/cacheflush.h> | |
0f7b332f | 25 | #include <asm/hardware/gic.h> |
2b12b5c4 CY |
26 | #include <asm/smp_scu.h> |
27 | #include <asm/unified.h> | |
28 | ||
29 | #include <mach/hardware.h> | |
30 | #include <mach/regs-clock.h> | |
911c29b0 | 31 | #include <mach/regs-pmu.h> |
2b12b5c4 | 32 | |
7d30e8b3 | 33 | extern void exynos4_secondary_startup(void); |
2b12b5c4 | 34 | |
911c29b0 JM |
35 | #define CPU1_BOOT_REG S5P_VA_SYSRAM |
36 | ||
2b12b5c4 CY |
37 | /* |
38 | * control for which core is the next to come out of the secondary | |
39 | * boot "holding pen" | |
40 | */ | |
41 | ||
42 | volatile int __cpuinitdata pen_release = -1; | |
43 | ||
3705ff6d RK |
44 | /* |
45 | * Write pen_release in a way that is guaranteed to be visible to all | |
46 | * observers, irrespective of whether they're taking part in coherency | |
47 | * or not. This is necessary for the hotplug code to work reliably. | |
48 | */ | |
49 | static void write_pen_release(int val) | |
50 | { | |
51 | pen_release = val; | |
52 | smp_wmb(); | |
53 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | |
54 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | |
55 | } | |
56 | ||
2b12b5c4 CY |
57 | static void __iomem *scu_base_addr(void) |
58 | { | |
59 | return (void __iomem *)(S5P_VA_SCU); | |
60 | } | |
61 | ||
62 | static DEFINE_SPINLOCK(boot_lock); | |
63 | ||
aab74d3e CY |
64 | static void __cpuinit exynos4_gic_secondary_init(void) |
65 | { | |
66 | void __iomem *dist_base = S5P_VA_GIC_DIST + | |
67 | (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); | |
68 | void __iomem *cpu_base = S5P_VA_GIC_CPU + | |
69 | (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); | |
70 | int i; | |
71 | ||
72 | /* | |
73 | * Deal with the banked PPI and SGI interrupts - disable all | |
74 | * PPI interrupts, ensure all SGI interrupts are enabled. | |
75 | */ | |
76 | __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); | |
77 | __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); | |
78 | ||
79 | /* | |
80 | * Set priority on PPI and SGI interrupts | |
81 | */ | |
82 | for (i = 0; i < 32; i += 4) | |
83 | __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); | |
84 | ||
85 | __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK); | |
86 | __raw_writel(1, cpu_base + GIC_CPU_CTRL); | |
87 | } | |
88 | ||
2b12b5c4 CY |
89 | void __cpuinit platform_secondary_init(unsigned int cpu) |
90 | { | |
2b12b5c4 CY |
91 | /* |
92 | * if any interrupts are already enabled for the primary | |
93 | * core (e.g. timer irq), then they will not have been enabled | |
94 | * for us: do so | |
95 | */ | |
aab74d3e | 96 | exynos4_gic_secondary_init(); |
2b12b5c4 CY |
97 | |
98 | /* | |
99 | * let the primary processor know we're out of the | |
100 | * pen, then head off into the C entry point | |
101 | */ | |
3705ff6d | 102 | write_pen_release(-1); |
2b12b5c4 CY |
103 | |
104 | /* | |
105 | * Synchronise with the boot thread. | |
106 | */ | |
107 | spin_lock(&boot_lock); | |
108 | spin_unlock(&boot_lock); | |
109 | } | |
110 | ||
111 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
112 | { | |
113 | unsigned long timeout; | |
114 | ||
115 | /* | |
116 | * Set synchronisation state between this boot processor | |
117 | * and the secondary one | |
118 | */ | |
119 | spin_lock(&boot_lock); | |
120 | ||
121 | /* | |
122 | * The secondary processor is waiting to be released from | |
123 | * the holding pen - release it, then wait for it to flag | |
124 | * that it has been released by resetting pen_release. | |
125 | * | |
126 | * Note that "pen_release" is the hardware CPU ID, whereas | |
127 | * "cpu" is Linux's internal ID. | |
128 | */ | |
3705ff6d | 129 | write_pen_release(cpu); |
2b12b5c4 | 130 | |
911c29b0 JM |
131 | if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) { |
132 | __raw_writel(S5P_CORE_LOCAL_PWR_EN, | |
133 | S5P_ARM_CORE1_CONFIGURATION); | |
134 | ||
135 | timeout = 10; | |
136 | ||
137 | /* wait max 10 ms until cpu1 is on */ | |
138 | while ((__raw_readl(S5P_ARM_CORE1_STATUS) | |
139 | & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) { | |
140 | if (timeout-- == 0) | |
141 | break; | |
142 | ||
143 | mdelay(1); | |
144 | } | |
145 | ||
146 | if (timeout == 0) { | |
147 | printk(KERN_ERR "cpu1 power enable failed"); | |
148 | spin_unlock(&boot_lock); | |
149 | return -ETIMEDOUT; | |
150 | } | |
151 | } | |
2b12b5c4 CY |
152 | /* |
153 | * Send the secondary CPU a soft interrupt, thereby causing | |
154 | * the boot monitor to read the system wide flags register, | |
155 | * and branch to the address found there. | |
156 | */ | |
2b12b5c4 CY |
157 | |
158 | timeout = jiffies + (1 * HZ); | |
159 | while (time_before(jiffies, timeout)) { | |
160 | smp_rmb(); | |
911c29b0 JM |
161 | |
162 | __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), | |
163 | CPU1_BOOT_REG); | |
164 | gic_raise_softirq(cpumask_of(cpu), 1); | |
165 | ||
2b12b5c4 CY |
166 | if (pen_release == -1) |
167 | break; | |
168 | ||
169 | udelay(10); | |
170 | } | |
171 | ||
172 | /* | |
173 | * now the secondary core is starting up let it run its | |
174 | * calibrations, then wait for it to finish | |
175 | */ | |
176 | spin_unlock(&boot_lock); | |
177 | ||
178 | return pen_release != -1 ? -ENOSYS : 0; | |
179 | } | |
180 | ||
181 | /* | |
182 | * Initialise the CPU possible map early - this describes the CPUs | |
183 | * which may be present or become present in the system. | |
184 | */ | |
185 | ||
186 | void __init smp_init_cpus(void) | |
187 | { | |
188 | void __iomem *scu_base = scu_base_addr(); | |
189 | unsigned int i, ncores; | |
190 | ||
191 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; | |
192 | ||
193 | /* sanity check */ | |
2b12b5c4 CY |
194 | if (ncores > NR_CPUS) { |
195 | printk(KERN_WARNING | |
7d30e8b3 | 196 | "EXYNOS4: no. of cores (%d) greater than configured " |
2b12b5c4 CY |
197 | "maximum of %d - clipping\n", |
198 | ncores, NR_CPUS); | |
199 | ncores = NR_CPUS; | |
200 | } | |
201 | ||
202 | for (i = 0; i < ncores; i++) | |
203 | set_cpu_possible(i, true); | |
0f7b332f RK |
204 | |
205 | set_smp_cross_call(gic_raise_softirq); | |
2b12b5c4 CY |
206 | } |
207 | ||
05c74a6c | 208 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
2b12b5c4 | 209 | { |
2b12b5c4 | 210 | |
05c74a6c RK |
211 | scu_enable(scu_base_addr()); |
212 | ||
2b12b5c4 | 213 | /* |
05c74a6c RK |
214 | * Write the address of secondary startup into the |
215 | * system-wide flags register. The boot monitor waits | |
216 | * until it receives a soft interrupt, and then the | |
217 | * secondary CPU branches to this address. | |
2b12b5c4 | 218 | */ |
7d30e8b3 | 219 | __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM); |
2b12b5c4 | 220 | } |