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1 | /* linux/arch/arm/mach-exynos4/mach-armlex4210.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/gpio.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/mmc/host.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/serial_core.h> | |
16 | #include <linux/smsc911x.h> | |
17 | ||
18 | #include <asm/mach/arch.h> | |
19 | #include <asm/mach-types.h> | |
20 | ||
21 | #include <plat/cpu.h> | |
22 | #include <plat/devs.h> | |
af6ec5a2 AA |
23 | #include <plat/gpio-cfg.h> |
24 | #include <plat/regs-serial.h> | |
25 | #include <plat/regs-srom.h> | |
26 | #include <plat/sdhci.h> | |
27 | ||
28 | #include <mach/map.h> | |
29 | ||
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30 | #include "common.h" |
31 | ||
af6ec5a2 AA |
32 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
33 | #define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | |
34 | S3C2410_UCON_RXILEVEL | \ | |
35 | S3C2410_UCON_TXIRQMODE | \ | |
36 | S3C2410_UCON_RXIRQMODE | \ | |
37 | S3C2410_UCON_RXFIFO_TOI | \ | |
38 | S3C2443_UCON_RXERR_IRQEN) | |
39 | ||
40 | #define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8 | |
41 | ||
42 | #define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | |
43 | S5PV210_UFCON_TXTRIG4 | \ | |
44 | S5PV210_UFCON_RXTRIG4) | |
45 | ||
46 | static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = { | |
47 | [0] = { | |
48 | .hwport = 0, | |
49 | .flags = 0, | |
50 | .ucon = ARMLEX4210_UCON_DEFAULT, | |
51 | .ulcon = ARMLEX4210_ULCON_DEFAULT, | |
52 | .ufcon = ARMLEX4210_UFCON_DEFAULT, | |
53 | }, | |
54 | [1] = { | |
55 | .hwport = 1, | |
56 | .flags = 0, | |
57 | .ucon = ARMLEX4210_UCON_DEFAULT, | |
58 | .ulcon = ARMLEX4210_ULCON_DEFAULT, | |
59 | .ufcon = ARMLEX4210_UFCON_DEFAULT, | |
60 | }, | |
61 | [2] = { | |
62 | .hwport = 2, | |
63 | .flags = 0, | |
64 | .ucon = ARMLEX4210_UCON_DEFAULT, | |
65 | .ulcon = ARMLEX4210_ULCON_DEFAULT, | |
66 | .ufcon = ARMLEX4210_UFCON_DEFAULT, | |
67 | }, | |
68 | [3] = { | |
69 | .hwport = 3, | |
70 | .flags = 0, | |
71 | .ucon = ARMLEX4210_UCON_DEFAULT, | |
72 | .ulcon = ARMLEX4210_ULCON_DEFAULT, | |
73 | .ufcon = ARMLEX4210_UFCON_DEFAULT, | |
74 | }, | |
75 | }; | |
76 | ||
77 | static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = { | |
78 | .cd_type = S3C_SDHCI_CD_PERMANENT, | |
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79 | #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT |
80 | .max_width = 8, | |
81 | .host_caps = MMC_CAP_8_BIT_DATA, | |
82 | #endif | |
83 | }; | |
84 | ||
85 | static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = { | |
86 | .cd_type = S3C_SDHCI_CD_GPIO, | |
87 | .ext_cd_gpio = EXYNOS4_GPX2(5), | |
88 | .ext_cd_gpio_invert = 1, | |
af6ec5a2 AA |
89 | .max_width = 4, |
90 | }; | |
91 | ||
92 | static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = { | |
93 | .cd_type = S3C_SDHCI_CD_PERMANENT, | |
af6ec5a2 AA |
94 | .max_width = 4, |
95 | }; | |
96 | ||
97 | static void __init armlex4210_sdhci_init(void) | |
98 | { | |
99 | s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata); | |
100 | s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata); | |
101 | s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata); | |
102 | } | |
103 | ||
104 | static void __init armlex4210_wlan_init(void) | |
105 | { | |
106 | /* enable */ | |
107 | s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf)); | |
108 | s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP); | |
109 | ||
110 | /* reset */ | |
111 | s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf)); | |
112 | s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP); | |
113 | ||
114 | /* wakeup */ | |
115 | s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf)); | |
116 | s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP); | |
117 | } | |
118 | ||
119 | static struct resource armlex4210_smsc911x_resources[] = { | |
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120 | [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K), |
121 | [1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \ | |
122 | | IRQF_TRIGGER_HIGH), | |
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123 | }; |
124 | ||
125 | static struct smsc911x_platform_config smsc9215_config = { | |
126 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, | |
127 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | |
128 | .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, | |
129 | .phy_interface = PHY_INTERFACE_MODE_MII, | |
130 | .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67}, | |
131 | }; | |
132 | ||
133 | static struct platform_device armlex4210_smsc911x = { | |
134 | .name = "smsc911x", | |
135 | .id = -1, | |
136 | .num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources), | |
137 | .resource = armlex4210_smsc911x_resources, | |
138 | .dev = { | |
139 | .platform_data = &smsc9215_config, | |
140 | }, | |
141 | }; | |
142 | ||
143 | static struct platform_device *armlex4210_devices[] __initdata = { | |
144 | &s3c_device_hsmmc0, | |
145 | &s3c_device_hsmmc2, | |
146 | &s3c_device_hsmmc3, | |
147 | &s3c_device_rtc, | |
148 | &s3c_device_wdt, | |
af6ec5a2 | 149 | &armlex4210_smsc911x, |
40360217 | 150 | &exynos4_device_ahci, |
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151 | }; |
152 | ||
153 | static void __init armlex4210_smsc911x_init(void) | |
154 | { | |
155 | u32 cs1; | |
156 | ||
157 | /* configure nCS1 width to 16 bits */ | |
158 | cs1 = __raw_readl(S5P_SROM_BW) & | |
159 | ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT); | |
160 | cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) | | |
161 | (0 << S5P_SROM_BW__WAITENABLE__SHIFT) | | |
162 | (1 << S5P_SROM_BW__ADDRMODE__SHIFT) | | |
163 | (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << | |
164 | S5P_SROM_BW__NCS1__SHIFT; | |
165 | __raw_writel(cs1, S5P_SROM_BW); | |
166 | ||
167 | /* set timing for nCS1 suitable for ethernet chip */ | |
168 | __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) | | |
169 | (0x9 << S5P_SROM_BCX__TACP__SHIFT) | | |
170 | (0xc << S5P_SROM_BCX__TCAH__SHIFT) | | |
171 | (0x1 << S5P_SROM_BCX__TCOH__SHIFT) | | |
172 | (0x6 << S5P_SROM_BCX__TACC__SHIFT) | | |
173 | (0x1 << S5P_SROM_BCX__TCOS__SHIFT) | | |
174 | (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); | |
175 | } | |
176 | ||
177 | static void __init armlex4210_map_io(void) | |
178 | { | |
cc511b8d | 179 | exynos_init_io(NULL, 0); |
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180 | s3c24xx_init_clocks(24000000); |
181 | s3c24xx_init_uarts(armlex4210_uartcfgs, | |
182 | ARRAY_SIZE(armlex4210_uartcfgs)); | |
183 | } | |
184 | ||
185 | static void __init armlex4210_machine_init(void) | |
186 | { | |
187 | armlex4210_smsc911x_init(); | |
188 | ||
189 | armlex4210_sdhci_init(); | |
190 | ||
191 | armlex4210_wlan_init(); | |
192 | ||
193 | platform_add_devices(armlex4210_devices, | |
194 | ARRAY_SIZE(armlex4210_devices)); | |
195 | } | |
196 | ||
197 | MACHINE_START(ARMLEX4210, "ARMLEX4210") | |
198 | /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */ | |
2be5a4a7 | 199 | .atag_offset = 0x100, |
06853ae4 | 200 | .smp = smp_ops(exynos_smp_ops), |
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201 | .init_irq = exynos4_init_irq, |
202 | .map_io = armlex4210_map_io, | |
203 | .init_machine = armlex4210_machine_init, | |
bb13fabc | 204 | .init_late = exynos_init_late, |
af6ec5a2 | 205 | .timer = &exynos4_timer, |
9eb48595 | 206 | .restart = exynos4_restart, |
af6ec5a2 | 207 | MACHINE_END |