Commit | Line | Data |
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edabd38e SB |
1 | /* |
2 | * arch/arm/mach-dove/pcie.c | |
3 | * | |
4 | * PCIe functions for Marvell Dove 88AP510 SoC | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/pci.h> | |
cc22b4c1 | 13 | #include <video/vga.h> |
edabd38e SB |
14 | #include <asm/mach/pci.h> |
15 | #include <asm/mach/arch.h> | |
16 | #include <asm/setup.h> | |
17 | #include <asm/delay.h> | |
18 | #include <plat/pcie.h> | |
19 | #include <mach/irqs.h> | |
20 | #include <mach/bridge-regs.h> | |
45173d5e | 21 | #include <plat/addr-map.h> |
edabd38e SB |
22 | #include "common.h" |
23 | ||
24 | struct pcie_port { | |
25 | u8 index; | |
26 | u8 root_bus_nr; | |
27 | void __iomem *base; | |
28 | spinlock_t conf_lock; | |
edabd38e | 29 | char mem_space_name[16]; |
d191bb69 | 30 | struct resource res; |
edabd38e SB |
31 | }; |
32 | ||
33 | static struct pcie_port pcie_port[2]; | |
34 | static int num_pcie_ports; | |
35 | ||
36 | ||
37 | static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) | |
38 | { | |
39 | struct pcie_port *pp; | |
40 | ||
41 | if (nr >= num_pcie_ports) | |
42 | return 0; | |
43 | ||
44 | pp = &pcie_port[nr]; | |
43ba990b | 45 | sys->private_data = pp; |
edabd38e SB |
46 | pp->root_bus_nr = sys->busnr; |
47 | ||
48 | /* | |
49 | * Generic PCIe unit setup. | |
50 | */ | |
51 | orion_pcie_set_local_bus_nr(pp->base, sys->busnr); | |
52 | ||
63a9332b | 53 | orion_pcie_setup(pp->base); |
edabd38e | 54 | |
d191bb69 RH |
55 | if (pp->index == 0) |
56 | pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE); | |
57 | else | |
58 | pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE); | |
edabd38e SB |
59 | |
60 | /* | |
61 | * IORESOURCE_MEM | |
62 | */ | |
63 | snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), | |
64 | "PCIe %d MEM", pp->index); | |
65 | pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; | |
d191bb69 | 66 | pp->res.name = pp->mem_space_name; |
edabd38e | 67 | if (pp->index == 0) { |
d191bb69 RH |
68 | pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE; |
69 | pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1; | |
edabd38e | 70 | } else { |
d191bb69 RH |
71 | pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE; |
72 | pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1; | |
edabd38e | 73 | } |
d191bb69 RH |
74 | pp->res.flags = IORESOURCE_MEM; |
75 | if (request_resource(&iomem_resource, &pp->res)) | |
edabd38e | 76 | panic("Request PCIe Memory resource failed\n"); |
d191bb69 | 77 | pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); |
edabd38e SB |
78 | |
79 | return 1; | |
80 | } | |
81 | ||
edabd38e SB |
82 | static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) |
83 | { | |
84 | /* | |
85 | * Don't go out when trying to access nonexisting devices | |
86 | * on the local bus. | |
87 | */ | |
88 | if (bus == pp->root_bus_nr && dev > 1) | |
89 | return 0; | |
90 | ||
91 | return 1; | |
92 | } | |
93 | ||
94 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | |
95 | int size, u32 *val) | |
96 | { | |
43ba990b RK |
97 | struct pci_sys_data *sys = bus->sysdata; |
98 | struct pcie_port *pp = sys->private_data; | |
edabd38e SB |
99 | unsigned long flags; |
100 | int ret; | |
101 | ||
102 | if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { | |
103 | *val = 0xffffffff; | |
104 | return PCIBIOS_DEVICE_NOT_FOUND; | |
105 | } | |
106 | ||
107 | spin_lock_irqsave(&pp->conf_lock, flags); | |
108 | ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); | |
109 | spin_unlock_irqrestore(&pp->conf_lock, flags); | |
110 | ||
111 | return ret; | |
112 | } | |
113 | ||
114 | static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, | |
115 | int where, int size, u32 val) | |
116 | { | |
43ba990b RK |
117 | struct pci_sys_data *sys = bus->sysdata; |
118 | struct pcie_port *pp = sys->private_data; | |
edabd38e SB |
119 | unsigned long flags; |
120 | int ret; | |
121 | ||
122 | if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) | |
123 | return PCIBIOS_DEVICE_NOT_FOUND; | |
124 | ||
125 | spin_lock_irqsave(&pp->conf_lock, flags); | |
126 | ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); | |
127 | spin_unlock_irqrestore(&pp->conf_lock, flags); | |
128 | ||
129 | return ret; | |
130 | } | |
131 | ||
132 | static struct pci_ops pcie_ops = { | |
133 | .read = pcie_rd_conf, | |
134 | .write = pcie_wr_conf, | |
135 | }; | |
136 | ||
137 | static void __devinit rc_pci_fixup(struct pci_dev *dev) | |
138 | { | |
139 | /* | |
140 | * Prevent enumeration of root complex. | |
141 | */ | |
142 | if (dev->bus->parent == NULL && dev->devfn == 0) { | |
143 | int i; | |
144 | ||
145 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
146 | dev->resource[i].start = 0; | |
147 | dev->resource[i].end = 0; | |
148 | dev->resource[i].flags = 0; | |
149 | } | |
150 | } | |
151 | } | |
152 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); | |
153 | ||
154 | static struct pci_bus __init * | |
155 | dove_pcie_scan_bus(int nr, struct pci_sys_data *sys) | |
156 | { | |
157 | struct pci_bus *bus; | |
158 | ||
159 | if (nr < num_pcie_ports) { | |
37d15909 BH |
160 | bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, |
161 | &sys->resources); | |
edabd38e SB |
162 | } else { |
163 | bus = NULL; | |
164 | BUG(); | |
165 | } | |
166 | ||
167 | return bus; | |
168 | } | |
169 | ||
d5341942 | 170 | static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
edabd38e | 171 | { |
43ba990b RK |
172 | struct pci_sys_data *sys = dev->sysdata; |
173 | struct pcie_port *pp = sys->private_data; | |
edabd38e SB |
174 | |
175 | return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0; | |
176 | } | |
177 | ||
178 | static struct hw_pci dove_pci __initdata = { | |
179 | .nr_controllers = 2, | |
edabd38e SB |
180 | .setup = dove_pcie_setup, |
181 | .scan = dove_pcie_scan_bus, | |
182 | .map_irq = dove_pcie_map_irq, | |
183 | }; | |
184 | ||
c3c5a281 | 185 | static void __init add_pcie_port(int index, void __iomem *base) |
edabd38e SB |
186 | { |
187 | printk(KERN_INFO "Dove PCIe port %d: ", index); | |
188 | ||
c3c5a281 | 189 | if (orion_pcie_link_up(base)) { |
edabd38e SB |
190 | struct pcie_port *pp = &pcie_port[num_pcie_ports++]; |
191 | ||
192 | printk(KERN_INFO "link up\n"); | |
193 | ||
194 | pp->index = index; | |
195 | pp->root_bus_nr = -1; | |
c3c5a281 | 196 | pp->base = base; |
edabd38e | 197 | spin_lock_init(&pp->conf_lock); |
d191bb69 | 198 | memset(&pp->res, 0, sizeof(pp->res)); |
edabd38e SB |
199 | } else { |
200 | printk(KERN_INFO "link down, ignoring\n"); | |
201 | } | |
202 | } | |
203 | ||
204 | void __init dove_pcie_init(int init_port0, int init_port1) | |
205 | { | |
cc22b4c1 RH |
206 | vga_base = DOVE_PCIE0_MEM_PHYS_BASE; |
207 | ||
edabd38e SB |
208 | if (init_port0) |
209 | add_pcie_port(0, DOVE_PCIE0_VIRT_BASE); | |
210 | ||
211 | if (init_port1) | |
212 | add_pcie_port(1, DOVE_PCIE1_VIRT_BASE); | |
213 | ||
214 | pci_common_init(&dove_pci); | |
215 | } |