[linux-2.6-block.git] / arch / arm / mach-dove / pcie.c

/*
 * arch/arm/mach-dove/pcie.c
 *
 * PCIe functions for Marvell Dove 88AP510 SoC
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
#include <asm/mach/pci.h>
#include <asm/mach/arch.h>
#include <asm/setup.h>
#include <asm/delay.h>
#include <plat/pcie.h>
#include <mach/irqs.h>
#include <mach/bridge-regs.h>
#include "common.h"

struct pcie_port {
	u8			index;
	u8			root_bus_nr;
	void __iomem		*base;
	spinlock_t		conf_lock;
	char			io_space_name[16];
	char			mem_space_name[16];
	struct resource		res[2];
};

static struct pcie_port pcie_port[2];
static int num_pcie_ports;


static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
{
	struct pcie_port *pp;

	if (nr >= num_pcie_ports)
		return 0;

	pp = &pcie_port[nr];
	pp->root_bus_nr = sys->busnr;

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);

	orion_pcie_setup(pp->base, &dove_mbus_dram_info);

	/*
	 * IORESOURCE_IO
	 */
	snprintf(pp->io_space_name, sizeof(pp->io_space_name),
		 "PCIe %d I/O", pp->index);
	pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
	pp->res[0].name = pp->io_space_name;
	if (pp->index == 0) {
		pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
		pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
	} else {
		pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
		pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
	}
	pp->res[0].flags = IORESOURCE_IO;
	if (request_resource(&ioport_resource, &pp->res[0]))
		panic("Request PCIe IO resource failed\n");
	sys->resource[0] = &pp->res[0];

	/*
	 * IORESOURCE_MEM
	 */
	snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
		 "PCIe %d MEM", pp->index);
	pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
	pp->res[1].name = pp->mem_space_name;
	if (pp->index == 0) {
		pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
		pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
	} else {
		pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
		pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
	}
	pp->res[1].flags = IORESOURCE_MEM;
	if (request_resource(&iomem_resource, &pp->res[1]))
		panic("Request PCIe Memory resource failed\n");
	sys->resource[1] = &pp->res[1];

	sys->resource[2] = NULL;

	return 1;
}

static struct pcie_port *bus_to_port(int bus)
{
	int i;

	for (i = num_pcie_ports - 1; i >= 0; i--) {
		int rbus = pcie_port[i].root_bus_nr;
		if (rbus != -1 && rbus <= bus)
			break;
	}

	return i >= 0 ? pcie_port + i : NULL;
}

static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
	/*
	 * Don't go out when trying to access nonexisting devices
	 * on the local bus.
	 */
	if (bus == pp->root_bus_nr && dev > 1)
		return 0;

	return 1;
}

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	struct pcie_port *pp = bus_to_port(bus->number);
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	struct pcie_port *pp = bus_to_port(bus->number);
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};

static void __devinit rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static struct pci_bus __init *
dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
{
	struct pci_bus *bus;

	if (nr < num_pcie_ports) {
		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	} else {
		bus = NULL;
		BUG();
	}

	return bus;
}

static int __init dove_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pcie_port *pp = bus_to_port(dev->bus->number);

	return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
}

static struct hw_pci dove_pci __initdata = {
	.nr_controllers	= 2,
	.swizzle	= pci_std_swizzle,
	.setup		= dove_pcie_setup,
	.scan		= dove_pcie_scan_bus,
	.map_irq	= dove_pcie_map_irq,
};

static void __init add_pcie_port(int index, unsigned long base)
{
	printk(KERN_INFO "Dove PCIe port %d: ", index);

	if (orion_pcie_link_up((void __iomem *)base)) {
		struct pcie_port *pp = &pcie_port[num_pcie_ports++];

		printk(KERN_INFO "link up\n");

		pp->index = index;
		pp->root_bus_nr = -1;
		pp->base = (void __iomem *)base;
		spin_lock_init(&pp->conf_lock);
		memset(pp->res, 0, sizeof(pp->res));
	} else {
		printk(KERN_INFO "link down, ignoring\n");
	}
}

void __init dove_pcie_init(int init_port0, int init_port1)
{
	if (init_port0)
		add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);

	if (init_port1)
		add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);

	pci_common_init(&dove_pci);
}
Commit	Line	Data
edabd38e SB	1	/*
	2	* arch/arm/mach-dove/pcie.c
	3	*
	4	* PCIe functions for Marvell Dove 88AP510 SoC
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/pci.h>
	13	#include <linux/mbus.h>
	14	#include <asm/mach/pci.h>
	15	#include <asm/mach/arch.h>
	16	#include <asm/setup.h>
	17	#include <asm/delay.h>
	18	#include <plat/pcie.h>
	19	#include <mach/irqs.h>
	20	#include <mach/bridge-regs.h>
	21	#include "common.h"
	22
	23	struct pcie_port {
	24	u8 index;
	25	u8 root_bus_nr;
	26	void __iomem *base;
	27	spinlock_t conf_lock;
	28	char io_space_name[16];
	29	char mem_space_name[16];
	30	struct resource res[2];
	31	};
	32
	33	static struct pcie_port pcie_port[2];
	34	static int num_pcie_ports;
	35
	36
	37	static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
	38	{
	39	struct pcie_port *pp;
	40
	41	if (nr >= num_pcie_ports)
	42	return 0;
	43
	44	pp = &pcie_port[nr];
	45	pp->root_bus_nr = sys->busnr;
	46
	47	/*
	48	* Generic PCIe unit setup.
	49	*/
	50	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
	51
	52	orion_pcie_setup(pp->base, &dove_mbus_dram_info);
	53
	54	/*
	55	* IORESOURCE_IO
	56	*/
	57	snprintf(pp->io_space_name, sizeof(pp->io_space_name),
	58	"PCIe %d I/O", pp->index);
	59	pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
	60	pp->res[0].name = pp->io_space_name;
	61	if (pp->index == 0) {
	62	pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
	63	pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
	64	} else {
65	pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
66	pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
67	}
68	pp->res[0].flags = IORESOURCE_IO;
69	if (request_resource(&ioport_resource, &pp->res[0]))
70	panic("Request PCIe IO resource failed\n");
71	sys->resource[0] = &pp->res[0];
72
73	/*
74	* IORESOURCE_MEM
75	*/
76	snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
77	"PCIe %d MEM", pp->index);
78	pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
79	pp->res[1].name = pp->mem_space_name;
80	if (pp->index == 0) {
81	pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
82	pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
83	} else {
84	pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
85	pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
86	}
87	pp->res[1].flags = IORESOURCE_MEM;
88	if (request_resource(&iomem_resource, &pp->res[1]))
89	panic("Request PCIe Memory resource failed\n");
90	sys->resource[1] = &pp->res[1];
91
92	sys->resource[2] = NULL;
93
94	return 1;
95	}
96
97	static struct pcie_port *bus_to_port(int bus)
98	{
99	int i;
100
101	for (i = num_pcie_ports - 1; i >= 0; i--) {
102	int rbus = pcie_port[i].root_bus_nr;
103	if (rbus != -1 && rbus <= bus)
104	break;
105	}
106
107	return i >= 0 ? pcie_port + i : NULL;
108	}
109
110	static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
111	{
112	/*
113	* Don't go out when trying to access nonexisting devices
114	* on the local bus.
115	*/
116	if (bus == pp->root_bus_nr && dev > 1)
117	return 0;
118
119	return 1;
120	}
121
122	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
123	int size, u32 *val)
124	{
125	struct pcie_port *pp = bus_to_port(bus->number);
126	unsigned long flags;
127	int ret;
128
129	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
130	*val = 0xffffffff;
131	return PCIBIOS_DEVICE_NOT_FOUND;
132	}
133
134	spin_lock_irqsave(&pp->conf_lock, flags);
135	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
136	spin_unlock_irqrestore(&pp->conf_lock, flags);
137
138	return ret;
139	}
140
141	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
142	int where, int size, u32 val)
143	{
144	struct pcie_port *pp = bus_to_port(bus->number);
145	unsigned long flags;
146	int ret;
147
148	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
149	return PCIBIOS_DEVICE_NOT_FOUND;
150
151	spin_lock_irqsave(&pp->conf_lock, flags);
152	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
153	spin_unlock_irqrestore(&pp->conf_lock, flags);
154
155	return ret;
156	}
157
158	static struct pci_ops pcie_ops = {
159	.read = pcie_rd_conf,
160	.write = pcie_wr_conf,
161	};
162
163	static void __devinit rc_pci_fixup(struct pci_dev *dev)
164	{
165	/*
166	* Prevent enumeration of root complex.
167	*/
168	if (dev->bus->parent == NULL && dev->devfn == 0) {
169	int i;
170
171	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
172	dev->resource[i].start = 0;
173	dev->resource[i].end = 0;
174	dev->resource[i].flags = 0;
175	}
176	}
177	}
178	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
179
180	static struct pci_bus __init *
181	dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
182	{
183	struct pci_bus *bus;
184
185	if (nr < num_pcie_ports) {
186	bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
187	} else {
188	bus = NULL;
189	BUG();
190	}
191
192	return bus;
193	}
194
195	static int __init dove_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
196	{
197	struct pcie_port *pp = bus_to_port(dev->bus->number);
198
199	return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
200	}
201
202	static struct hw_pci dove_pci __initdata = {
203	.nr_controllers = 2,
204	.swizzle = pci_std_swizzle,
205	.setup = dove_pcie_setup,
206	.scan = dove_pcie_scan_bus,
207	.map_irq = dove_pcie_map_irq,
208	};
209
210	static void __init add_pcie_port(int index, unsigned long base)
211	{
212	printk(KERN_INFO "Dove PCIe port %d: ", index);
213
214	if (orion_pcie_link_up((void __iomem *)base)) {
215	struct pcie_port *pp = &pcie_port[num_pcie_ports++];
216
217	printk(KERN_INFO "link up\n");
218
219	pp->index = index;
220	pp->root_bus_nr = -1;
221	pp->base = (void __iomem *)base;
222	spin_lock_init(&pp->conf_lock);
223	memset(pp->res, 0, sizeof(pp->res));
224	} else {
225	printk(KERN_INFO "link down, ignoring\n");
226	}
227	}
228
229	void __init dove_pcie_init(int init_port0, int init_port1)
230	{
231	if (init_port0)
232	add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
233
234	if (init_port1)
235	add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
236
237	pci_common_init(&dove_pci);
238	}