[linux-2.6-block.git] / arch / arm / mach-dove / common.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * arch/arm/mach-dove/common.c
 *
 * Core functions for Marvell Dove 88AP510 System On Chip
 */

#include <linux/clk-provider.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_data/dma-mv_xor.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <linux/platform_device.h>
#include <linux/soc/dove/pmu.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <plat/common.h>
#include <plat/irq.h>
#include <plat/time.h>
#include "bridge-regs.h"
#include "pm.h"
#include "common.h"

/* These can go away once Dove uses the mvebu-mbus DT binding */
#define DOVE_MBUS_PCIE0_MEM_TARGET    0x4
#define DOVE_MBUS_PCIE0_MEM_ATTR      0xe8
#define DOVE_MBUS_PCIE0_IO_TARGET     0x4
#define DOVE_MBUS_PCIE0_IO_ATTR       0xe0
#define DOVE_MBUS_PCIE1_MEM_TARGET    0x8
#define DOVE_MBUS_PCIE1_MEM_ATTR      0xe8
#define DOVE_MBUS_PCIE1_IO_TARGET     0x8
#define DOVE_MBUS_PCIE1_IO_ATTR       0xe0
#define DOVE_MBUS_CESA_TARGET         0x3
#define DOVE_MBUS_CESA_ATTR           0x1
#define DOVE_MBUS_BOOTROM_TARGET      0x1
#define DOVE_MBUS_BOOTROM_ATTR        0xfd
#define DOVE_MBUS_SCRATCHPAD_TARGET   0xd
#define DOVE_MBUS_SCRATCHPAD_ATTR     0x0

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc __maybe_unused dove_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long) DOVE_SB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
		.length		= DOVE_SB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long) DOVE_NB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
		.length		= DOVE_NB_REGS_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init dove_map_io(void)
{
	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
}

/*****************************************************************************
 * CLK tree
 ****************************************************************************/
static int dove_tclk;

static DEFINE_SPINLOCK(gating_lock);
static struct clk *tclk;

static struct clk __init *dove_register_gate(const char *name,
					     const char *parent, u8 bit_idx)
{
	return clk_register_gate(NULL, name, parent, 0,
				 (void __iomem *)CLOCK_GATING_CONTROL,
				 bit_idx, 0, &gating_lock);
}

static void __init dove_clk_init(void)
{
	struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
	struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
	struct clk *xor0, *xor1, *ge;

	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk);

	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
	pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
	dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);

	orion_clkdev_add(NULL, "orion_spi.0", tclk);
	orion_clkdev_add(NULL, "orion_spi.1", tclk);
	orion_clkdev_add(NULL, "orion_wdt", tclk);
	orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);

	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
	orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
	orion_clkdev_add(NULL, "sata_mv.0", sata);
	orion_clkdev_add("0", "pcie", pex0);
	orion_clkdev_add("1", "pcie", pex1);
	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
	orion_clkdev_add(NULL, "orion_nand", nand);
	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
	orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
	orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
	orion_clkdev_add(NULL, "mv_crypto", crypto);
	orion_clkdev_add(NULL, "dove-ac97", ac97);
	orion_clkdev_add(NULL, "dove-pdma", pdma);
	orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
	orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
}

/*****************************************************************************
 * EHCI0
 ****************************************************************************/
void __init dove_ehci0_init(void)
{
	orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
}

/*****************************************************************************
 * EHCI1
 ****************************************************************************/
void __init dove_ehci1_init(void)
{
	orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
}

/*****************************************************************************
 * GE00
 ****************************************************************************/
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
			IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
			1600);
}

/*****************************************************************************
 * SoC RTC
 ****************************************************************************/
static void __init dove_rtc_init(void)
{
	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}

/*****************************************************************************
 * SATA
 ****************************************************************************/
void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
	orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);

}

/*****************************************************************************
 * UART0
 ****************************************************************************/
void __init dove_uart0_init(void)
{
	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
			 IRQ_DOVE_UART_0, tclk);
}

/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init dove_uart1_init(void)
{
	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
			 IRQ_DOVE_UART_1, tclk);
}

/*****************************************************************************
 * UART2
 ****************************************************************************/
void __init dove_uart2_init(void)
{
	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
			 IRQ_DOVE_UART_2, tclk);
}

/*****************************************************************************
 * UART3
 ****************************************************************************/
void __init dove_uart3_init(void)
{
	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
			 IRQ_DOVE_UART_3, tclk);
}

/*****************************************************************************
 * SPI
 ****************************************************************************/
void __init dove_spi0_init(void)
{
	orion_spi_init(DOVE_SPI0_PHYS_BASE);
}

void __init dove_spi1_init(void)
{
	orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
}

/*****************************************************************************
 * I2C
 ****************************************************************************/
void __init dove_i2c_init(void)
{
	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
}

/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init dove_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
	mvebu_mbus_init("marvell,dove-mbus",
			BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
			DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
}

static int __init dove_find_tclk(void)
{
	return 166666667;
}

void __init dove_timer_init(void)
{
	dove_tclk = dove_find_tclk();
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_DOVE_BRIDGE, dove_tclk);
}

/*****************************************************************************
 * XOR 0
 ****************************************************************************/
static void __init dove_xor0_init(void)
{
	orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
			IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
}

/*****************************************************************************
 * XOR 1
 ****************************************************************************/
static void __init dove_xor1_init(void)
{
	orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
			IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
}

/*****************************************************************************
 * SDIO
 ****************************************************************************/
static u64 sdio_dmamask = DMA_BIT_MASK(32);

static struct resource dove_sdio0_resources[] = {
	{
		.start	= DOVE_SDIO0_PHYS_BASE,
		.end	= DOVE_SDIO0_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO0,
		.end	= IRQ_DOVE_SDIO0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio0 = {
	.name		= "sdhci-dove",
	.id		= 0,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio0_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio0_resources),
};

void __init dove_sdio0_init(void)
{
	platform_device_register(&dove_sdio0);
}

static struct resource dove_sdio1_resources[] = {
	{
		.start	= DOVE_SDIO1_PHYS_BASE,
		.end	= DOVE_SDIO1_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO1,
		.end	= IRQ_DOVE_SDIO1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio1 = {
	.name		= "sdhci-dove",
	.id		= 1,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio1_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio1_resources),
};

void __init dove_sdio1_init(void)
{
	platform_device_register(&dove_sdio1);
}

void __init dove_setup_cpu_wins(void)
{
	/*
	 * The PCIe windows will no longer be statically allocated
	 * here once Dove is migrated to the pci-mvebu driver. The
	 * non-PCIe windows will no longer be created here once Dove
	 * fully moves to DT.
	 */
	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
					  DOVE_MBUS_PCIE0_IO_ATTR,
					  DOVE_PCIE0_IO_PHYS_BASE,
					  DOVE_PCIE0_IO_SIZE,
					  DOVE_PCIE0_IO_BUS_BASE);
	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
					  DOVE_MBUS_PCIE1_IO_ATTR,
					  DOVE_PCIE1_IO_PHYS_BASE,
					  DOVE_PCIE1_IO_SIZE,
					  DOVE_PCIE1_IO_BUS_BASE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
				    DOVE_MBUS_PCIE0_MEM_ATTR,
				    DOVE_PCIE0_MEM_PHYS_BASE,
				    DOVE_PCIE0_MEM_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
				    DOVE_MBUS_PCIE1_MEM_ATTR,
				    DOVE_PCIE1_MEM_PHYS_BASE,
				    DOVE_PCIE1_MEM_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
				    DOVE_MBUS_CESA_ATTR,
				    DOVE_CESA_PHYS_BASE,
				    DOVE_CESA_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
				    DOVE_MBUS_BOOTROM_ATTR,
				    DOVE_BOOTROM_PHYS_BASE,
				    DOVE_BOOTROM_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
				    DOVE_MBUS_SCRATCHPAD_ATTR,
				    DOVE_SCRATCHPAD_PHYS_BASE,
				    DOVE_SCRATCHPAD_SIZE);
}

static struct resource orion_wdt_resource[] = {
		DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
		DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
};

static struct platform_device orion_wdt_device = {
	.name		= "orion_wdt",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(orion_wdt_resource),
	.resource	= orion_wdt_resource,
};

static void __init __maybe_unused orion_wdt_init(void)
{
	platform_device_register(&orion_wdt_device);
}

static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = {
	{
		.pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
		.rst_mask = PMU_SW_RST_VIDEO_MASK,
		.iso_mask = PMU_ISO_VIDEO_MASK,
		.name = "vpu-domain",
	}, {
		.pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
		.rst_mask = PMU_SW_RST_GPU_MASK,
		.iso_mask = PMU_ISO_GPU_MASK,
		.name = "gpu-domain",
	}, {
		/* sentinel */
	},
};

static const struct dove_pmu_initdata pmu_data __initconst = {
	.pmc_base = DOVE_PMU_VIRT_BASE,
	.pmu_base = DOVE_PMU_VIRT_BASE + 0x8000,
	.irq = IRQ_DOVE_PMU,
	.irq_domain_start = IRQ_DOVE_PMU_START,
	.domains = pmu_domains,
};

void __init dove_init(void)
{
	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
		(dove_tclk + 499999) / 1000000);

#ifdef CONFIG_CACHE_TAUROS2
	tauros2_init(0);
#endif
	dove_setup_cpu_wins();

	/* Setup root of clk tree */
	dove_clk_init();

	/* internal devices that every board has */
	dove_init_pmu_legacy(&pmu_data);
	dove_rtc_init();
	dove_xor0_init();
	dove_xor1_init();
}

void dove_restart(enum reboot_mode mode, const char *cmd)
{
	/*
	 * Enable soft reset to assert RSTOUTn.
	 */
	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);

	/*
	 * Assert soft reset.
	 */
	writel(SOFT_RESET, SYSTEM_SOFT_RESET);

	while (1)
		;
}
Commit	Line	Data
0fdebc5e	1	// SPDX-License-Identifier: GPL-2.0-only
edabd38e SB	2	/*
	3	* arch/arm/mach-dove/common.c
	4	*
	5	* Core functions for Marvell Dove 88AP510 System On Chip
edabd38e SB	6	*/
edabd38e SB	7
2f129bf4	8	#include <linux/clk-provider.h>
b3af7a1f SH	9	#include <linux/dma-mapping.h>
b3af7a1f SH	10	#include <linux/init.h>
62e59c4e	11	#include <linux/io.h>
b3af7a1f SH	12	#include <linux/platform_data/dma-mv_xor.h>
	13	#include <linux/platform_data/usb-ehci-orion.h>
	14	#include <linux/platform_device.h>
c5d431e8	15	#include <linux/soc/dove/pmu.h>
573a652f	16	#include <asm/hardware/cache-tauros2.h>
b3af7a1f	17	#include <asm/mach/arch.h>
edabd38e SB	18	#include <asm/mach/map.h>
edabd38e SB	19	#include <asm/mach/time.h>
28a2b450	20	#include <plat/common.h>
b3af7a1f SH	21	#include <plat/irq.h>
b3af7a1f SH	22	#include <plat/time.h>
ce78179e AB	23	#include "bridge-regs.h"
ce78179e AB	24	#include "pm.h"
edabd38e SB	25	#include "common.h"
edabd38e SB	26
89a7fbfb TP	27	/* These can go away once Dove uses the mvebu-mbus DT binding */
	28	#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4
	29	#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8
	30	#define DOVE_MBUS_PCIE0_IO_TARGET 0x4
	31	#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0
	32	#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8
	33	#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8
	34	#define DOVE_MBUS_PCIE1_IO_TARGET 0x8
	35	#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0
	36	#define DOVE_MBUS_CESA_TARGET 0x3
	37	#define DOVE_MBUS_CESA_ATTR 0x1
	38	#define DOVE_MBUS_BOOTROM_TARGET 0x1
	39	#define DOVE_MBUS_BOOTROM_ATTR 0xfd
	40	#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd
	41	#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0
	42
edabd38e SB	43	/*****************************************************************************
	44	* I/O Address Mapping
	45	****************************************************************************/
afb80cf1	46	static struct map_desc __maybe_unused dove_io_desc[] __initdata = {
edabd38e	47	{
c3c5a281	48	.virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
edabd38e SB	49	.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
	50	.length = DOVE_SB_REGS_SIZE,
	51	.type = MT_DEVICE,
	52	}, {
c3c5a281	53	.virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
edabd38e SB	54	.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
	55	.length = DOVE_NB_REGS_SIZE,
	56	.type = MT_DEVICE,
edabd38e SB	57	},
	58	};
	59
	60	void __init dove_map_io(void)
	61	{
	62	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
	63	}
	64
2f129bf4 AL	65	/*****************************************************************************
	66	* CLK tree
	67	****************************************************************************/
5817d10b	68	static int dove_tclk;
52167471 SH	69
52167471 SH	70	static DEFINE_SPINLOCK(gating_lock);
2f129bf4 AL	71	static struct clk *tclk;
2f129bf4 AL	72
52167471 SH	73	static struct clk __init dove_register_gate(const char name,
52167471 SH	74	const char *parent, u8 bit_idx)
2f129bf4	75	{
52167471 SH	76	return clk_register_gate(NULL, name, parent, 0,
	77	(void __iomem *)CLOCK_GATING_CONTROL,
	78	bit_idx, 0, &gating_lock);
	79	}
	80
5817d10b	81	static void __init dove_clk_init(void)
2f129bf4	82	{
52167471 SH	83	struct clk usb0, usb1, sata, pex0, pex1, sdio0, *sdio1;
52167471 SH	84	struct clk nand, camera, i2s0, i2s1, crypto, ac97, *pdma;
dea56c78	85	struct clk xor0, xor1, *ge;
4574b886	86
3a1a4559	87	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk);
4574b886	88
52167471 SH	89	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
	90	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
	91	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
	92	pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
	93	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
	94	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
	95	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
	96	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
	97	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
	98	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
	99	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
	100	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
	101	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
	102	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
	103	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
	104	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
dea56c78	105	dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
52167471 SH	106	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
	107
	108	orion_clkdev_add(NULL, "orion_spi.0", tclk);
	109	orion_clkdev_add(NULL, "orion_spi.1", tclk);
	110	orion_clkdev_add(NULL, "orion_wdt", tclk);
	111	orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
	112
	113	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
	114	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
3fbcd3d0 SH	115	orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
3fbcd3d0 SH	116	orion_clkdev_add(NULL, "sata_mv.0", sata);
52167471 SH	117	orion_clkdev_add("0", "pcie", pex0);
	118	orion_clkdev_add("1", "pcie", pex1);
	119	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
	120	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
	121	orion_clkdev_add(NULL, "orion_nand", nand);
	122	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
64ddf1f8 RK	123	orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
64ddf1f8 RK	124	orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
52167471 SH	125	orion_clkdev_add(NULL, "mv_crypto", crypto);
	126	orion_clkdev_add(NULL, "dove-ac97", ac97);
	127	orion_clkdev_add(NULL, "dove-pdma", pdma);
0dddee7a TP	128	orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
0dddee7a TP	129	orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
2f129bf4 AL	130	}
2f129bf4 AL	131
edabd38e SB	132	/*****************************************************************************
	133	* EHCI0
	134	****************************************************************************/
edabd38e SB	135	void __init dove_ehci0_init(void)
edabd38e SB	136	{
72053353	137	orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
edabd38e SB	138	}
	139
	140	/*****************************************************************************
	141	* EHCI1
	142	****************************************************************************/
edabd38e SB	143	void __init dove_ehci1_init(void)
edabd38e SB	144	{
db33f4de	145	orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
edabd38e SB	146	}
	147
	148	/*****************************************************************************
	149	* GE00
	150	****************************************************************************/
edabd38e SB	151	void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
edabd38e SB	152	{
30e0f580	153	orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
58569aee APR	154	IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
58569aee APR	155	1600);
edabd38e SB	156	}
	157
	158	/*****************************************************************************
	159	* SoC RTC
	160	****************************************************************************/
887c206a	161	static void __init dove_rtc_init(void)
edabd38e	162	{
f6eaccb3	163	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
edabd38e SB	164	}
	165
	166	/*****************************************************************************
	167	* SATA
	168	****************************************************************************/
edabd38e SB	169	void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
edabd38e SB	170	{
db33f4de	171	orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
9e613f8a	172
edabd38e SB	173	}
	174
	175	/*****************************************************************************
	176	* UART0
	177	****************************************************************************/
edabd38e SB	178	void __init dove_uart0_init(void)
edabd38e SB	179	{
28a2b450	180	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
74c33576	181	IRQ_DOVE_UART_0, tclk);
edabd38e SB	182	}
	183
	184	/*****************************************************************************
	185	* UART1
	186	****************************************************************************/
edabd38e SB	187	void __init dove_uart1_init(void)
edabd38e SB	188	{
28a2b450	189	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
74c33576	190	IRQ_DOVE_UART_1, tclk);
edabd38e SB	191	}
	192
	193	/*****************************************************************************
	194	* UART2
	195	****************************************************************************/
edabd38e SB	196	void __init dove_uart2_init(void)
edabd38e SB	197	{
28a2b450	198	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
74c33576	199	IRQ_DOVE_UART_2, tclk);
edabd38e SB	200	}
	201
	202	/*****************************************************************************
	203	* UART3
	204	****************************************************************************/
edabd38e SB	205	void __init dove_uart3_init(void)
edabd38e SB	206	{
28a2b450	207	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
74c33576	208	IRQ_DOVE_UART_3, tclk);
edabd38e SB	209	}
	210
	211	/*****************************************************************************
980f9f60	212	* SPI
edabd38e	213	****************************************************************************/
edabd38e SB	214	void __init dove_spi0_init(void)
edabd38e SB	215	{
4574b886	216	orion_spi_init(DOVE_SPI0_PHYS_BASE);
edabd38e SB	217	}
edabd38e SB	218
edabd38e SB	219	void __init dove_spi1_init(void)
edabd38e SB	220	{
4574b886	221	orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
edabd38e SB	222	}
	223
	224	/*****************************************************************************
	225	* I2C
	226	****************************************************************************/
edabd38e SB	227	void __init dove_i2c_init(void)
edabd38e SB	228	{
aac7ffa3	229	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
edabd38e SB	230	}
	231
	232	/*****************************************************************************
	233	* Time handling
	234	****************************************************************************/
4ee1f6b5 LB	235	void __init dove_init_early(void)
	236	{
	237	orion_time_set_base(TIMER_VIRT_BASE);
7d554902 TP	238	mvebu_mbus_init("marvell,dove-mbus",
	239	BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
	240	DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
4ee1f6b5 LB	241	}
4ee1f6b5 LB	242
5817d10b	243	static int __init dove_find_tclk(void)
edabd38e	244	{
edabd38e SB	245	return 166666667;
	246	}
	247
6bb27d73	248	void __init dove_timer_init(void)
edabd38e	249	{
5817d10b	250	dove_tclk = dove_find_tclk();
4ee1f6b5	251	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
5817d10b	252	IRQ_DOVE_BRIDGE, dove_tclk);
edabd38e SB	253	}
edabd38e SB	254
edabd38e SB	255	/*****************************************************************************
	256	* XOR 0
	257	****************************************************************************/
887c206a	258	static void __init dove_xor0_init(void)
edabd38e	259	{
db33f4de	260	orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
ee962723	261	IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
edabd38e SB	262	}
	263
	264	/*****************************************************************************
	265	* XOR 1
	266	****************************************************************************/
887c206a	267	static void __init dove_xor1_init(void)
edabd38e	268	{
ee962723 AL	269	orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
ee962723 AL	270	IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
edabd38e SB	271	}
edabd38e SB	272
16bc90af SB	273	/*****************************************************************************
	274	* SDIO
	275	****************************************************************************/
	276	static u64 sdio_dmamask = DMA_BIT_MASK(32);
	277
	278	static struct resource dove_sdio0_resources[] = {
	279	{
	280	.start = DOVE_SDIO0_PHYS_BASE,
	281	.end = DOVE_SDIO0_PHYS_BASE + 0xff,
	282	.flags = IORESOURCE_MEM,
	283	}, {
	284	.start = IRQ_DOVE_SDIO0,
	285	.end = IRQ_DOVE_SDIO0,
	286	.flags = IORESOURCE_IRQ,
	287	},
	288	};
	289
	290	static struct platform_device dove_sdio0 = {
930e2fe7	291	.name = "sdhci-dove",
16bc90af SB	292	.id = 0,
	293	.dev = {
	294	.dma_mask = &sdio_dmamask,
	295	.coherent_dma_mask = DMA_BIT_MASK(32),
	296	},
	297	.resource = dove_sdio0_resources,
	298	.num_resources = ARRAY_SIZE(dove_sdio0_resources),
	299	};
	300
	301	void __init dove_sdio0_init(void)
	302	{
	303	platform_device_register(&dove_sdio0);
	304	}
	305
	306	static struct resource dove_sdio1_resources[] = {
	307	{
	308	.start = DOVE_SDIO1_PHYS_BASE,
	309	.end = DOVE_SDIO1_PHYS_BASE + 0xff,
	310	.flags = IORESOURCE_MEM,
	311	}, {
	312	.start = IRQ_DOVE_SDIO1,
	313	.end = IRQ_DOVE_SDIO1,
	314	.flags = IORESOURCE_IRQ,
	315	},
	316	};
	317
	318	static struct platform_device dove_sdio1 = {
930e2fe7	319	.name = "sdhci-dove",
16bc90af SB	320	.id = 1,
	321	.dev = {
	322	.dma_mask = &sdio_dmamask,
	323	.coherent_dma_mask = DMA_BIT_MASK(32),
	324	},
	325	.resource = dove_sdio1_resources,
	326	.num_resources = ARRAY_SIZE(dove_sdio1_resources),
	327	};
	328
	329	void __init dove_sdio1_init(void)
	330	{
	331	platform_device_register(&dove_sdio1);
	332	}
	333
7d554902 TP	334	void __init dove_setup_cpu_wins(void)
	335	{
	336	/*
	337	* The PCIe windows will no longer be statically allocated
89a7fbfb TP	338	* here once Dove is migrated to the pci-mvebu driver. The
	339	* non-PCIe windows will no longer be created here once Dove
	340	* fully moves to DT.
7d554902	341	*/
89a7fbfb TP	342	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
89a7fbfb TP	343	DOVE_MBUS_PCIE0_IO_ATTR,
7d554902 TP	344	DOVE_PCIE0_IO_PHYS_BASE,
7d554902 TP	345	DOVE_PCIE0_IO_SIZE,
89a7fbfb TP	346	DOVE_PCIE0_IO_BUS_BASE);
	347	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
	348	DOVE_MBUS_PCIE1_IO_ATTR,
7d554902 TP	349	DOVE_PCIE1_IO_PHYS_BASE,
7d554902 TP	350	DOVE_PCIE1_IO_SIZE,
89a7fbfb TP	351	DOVE_PCIE1_IO_BUS_BASE);
	352	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
	353	DOVE_MBUS_PCIE0_MEM_ATTR,
	354	DOVE_PCIE0_MEM_PHYS_BASE,
	355	DOVE_PCIE0_MEM_SIZE);
	356	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
	357	DOVE_MBUS_PCIE1_MEM_ATTR,
	358	DOVE_PCIE1_MEM_PHYS_BASE,
	359	DOVE_PCIE1_MEM_SIZE);
	360	mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
	361	DOVE_MBUS_CESA_ATTR,
	362	DOVE_CESA_PHYS_BASE,
	363	DOVE_CESA_SIZE);
	364	mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
	365	DOVE_MBUS_BOOTROM_ATTR,
	366	DOVE_BOOTROM_PHYS_BASE,
	367	DOVE_BOOTROM_SIZE);
	368	mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
	369	DOVE_MBUS_SCRATCHPAD_ATTR,
	370	DOVE_SCRATCHPAD_PHYS_BASE,
	371	DOVE_SCRATCHPAD_SIZE);
7d554902 TP	372	}
7d554902 TP	373
06f3008a AB	374	static struct resource orion_wdt_resource[] = {
	375	DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
	376	DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
	377	};
	378
	379	static struct platform_device orion_wdt_device = {
	380	.name = "orion_wdt",
	381	.id = -1,
	382	.num_resources = ARRAY_SIZE(orion_wdt_resource),
	383	.resource = orion_wdt_resource,
	384	};
	385
	386	static void __init __maybe_unused orion_wdt_init(void)
	387	{
	388	platform_device_register(&orion_wdt_device);
	389	}
	390
c5d431e8 RK	391	static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = {
	392	{
	393	.pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
	394	.rst_mask = PMU_SW_RST_VIDEO_MASK,
	395	.iso_mask = PMU_ISO_VIDEO_MASK,
	396	.name = "vpu-domain",
	397	}, {
	398	.pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
	399	.rst_mask = PMU_SW_RST_GPU_MASK,
	400	.iso_mask = PMU_ISO_GPU_MASK,
	401	.name = "gpu-domain",
	402	}, {
	403	/* sentinel */
	404	},
	405	};
	406
	407	static const struct dove_pmu_initdata pmu_data __initconst = {
	408	.pmc_base = DOVE_PMU_VIRT_BASE,
	409	.pmu_base = DOVE_PMU_VIRT_BASE + 0x8000,
	410	.irq = IRQ_DOVE_PMU,
	411	.irq_domain_start = IRQ_DOVE_PMU_START,
	412	.domains = pmu_domains,
	413	};
	414
edabd38e SB	415	void __init dove_init(void)
edabd38e SB	416	{
5817d10b SH	417	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
5817d10b SH	418	(dove_tclk + 499999) / 1000000);
edabd38e	419
573a652f	420	#ifdef CONFIG_CACHE_TAUROS2
5cc58157	421	tauros2_init(0);
573a652f	422	#endif
7d554902	423	dove_setup_cpu_wins();
edabd38e	424
2f129bf4	425	/* Setup root of clk tree */
5817d10b	426	dove_clk_init();
2f129bf4	427
edabd38e	428	/* internal devices that every board has */
c5d431e8	429	dove_init_pmu_legacy(&pmu_data);
edabd38e SB	430	dove_rtc_init();
	431	dove_xor0_init();
	432	dove_xor1_init();
	433	}
6ca6ff97	434
7b6d864b	435	void dove_restart(enum reboot_mode mode, const char *cmd)
6ca6ff97 RK	436	{
	437	/*
	438	* Enable soft reset to assert RSTOUTn.
	439	*/
	440	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
	441
	442	/*
	443	* Assert soft reset.
	444	*/
	445	writel(SOFT_RESET, SYSTEM_SOFT_RESET);
	446
	447	while (1)
	448	;
	449	}