[linux-2.6-block.git] / arch / arm / mach-dove / common.c

/*
 * arch/arm/mach-dove/common.c
 *
 * Core functions for Marvell Dove 88AP510 System On Chip
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/serial_8250.h>
#include <linux/clk.h>
#include <linux/mbus.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/serial_8250.h>
#include <linux/spi/orion_spi.h>
#include <linux/gpio.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/pci.h>
#include <mach/dove.h>
#include <mach/bridge-regs.h>
#include <asm/mach/arch.h>
#include <linux/irq.h>
#include <plat/mv_xor.h>
#include <plat/ehci-orion.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"

static int get_tclk(void);

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc dove_io_desc[] __initdata = {
	{
		.virtual	= DOVE_SB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
		.length		= DOVE_SB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_NB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
		.length		= DOVE_NB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_PCIE0_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
		.length		= DOVE_PCIE0_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_PCIE1_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
		.length		= DOVE_PCIE1_IO_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init dove_map_io(void)
{
	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
}

/*****************************************************************************
 * EHCI
 ****************************************************************************/
static struct orion_ehci_data dove_ehci_data = {
	.dram		= &dove_mbus_dram_info,
	.phy_version	= EHCI_PHY_NA,
};

static u64 ehci_dmamask = DMA_BIT_MASK(32);

/*****************************************************************************
 * EHCI0
 ****************************************************************************/
static struct resource dove_ehci0_resources[] = {
	{
		.start	= DOVE_USB0_PHYS_BASE,
		.end	= DOVE_USB0_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_USB0,
		.end	= IRQ_DOVE_USB0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_ehci0 = {
	.name		= "orion-ehci",
	.id		= 0,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
		.platform_data		= &dove_ehci_data,
	},
	.resource	= dove_ehci0_resources,
	.num_resources	= ARRAY_SIZE(dove_ehci0_resources),
};

void __init dove_ehci0_init(void)
{
	platform_device_register(&dove_ehci0);
}

/*****************************************************************************
 * EHCI1
 ****************************************************************************/
static struct resource dove_ehci1_resources[] = {
	{
		.start	= DOVE_USB1_PHYS_BASE,
		.end	= DOVE_USB1_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_USB1,
		.end	= IRQ_DOVE_USB1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_ehci1 = {
	.name		= "orion-ehci",
	.id		= 1,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
		.platform_data		= &dove_ehci_data,
	},
	.resource	= dove_ehci1_resources,
	.num_resources	= ARRAY_SIZE(dove_ehci1_resources),
};

void __init dove_ehci1_init(void)
{
	platform_device_register(&dove_ehci1);
}

/*****************************************************************************
 * GE00
 ****************************************************************************/
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge00_init(eth_data, &dove_mbus_dram_info,
			DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
			0, get_tclk());
}

/*****************************************************************************
 * SoC RTC
 ****************************************************************************/
void __init dove_rtc_init(void)
{
	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}

/*****************************************************************************
 * SATA
 ****************************************************************************/
static struct resource dove_sata_resources[] = {
	{
		.name	= "sata base",
		.start	= DOVE_SATA_PHYS_BASE,
		.end	= DOVE_SATA_PHYS_BASE + 0x5000 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "sata irq",
		.start	= IRQ_DOVE_SATA,
		.end	= IRQ_DOVE_SATA,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sata = {
	.name		= "sata_mv",
	.id		= 0,
	.dev		= {
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.num_resources	= ARRAY_SIZE(dove_sata_resources),
	.resource	= dove_sata_resources,
};

void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
	sata_data->dram = &dove_mbus_dram_info;
	dove_sata.dev.platform_data = sata_data;
	platform_device_register(&dove_sata);
}

/*****************************************************************************
 * UART0
 ****************************************************************************/
void __init dove_uart0_init(void)
{
	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
			 IRQ_DOVE_UART_0, get_tclk());
}

/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init dove_uart1_init(void)
{
	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
			 IRQ_DOVE_UART_1, get_tclk());
}

/*****************************************************************************
 * UART2
 ****************************************************************************/
void __init dove_uart2_init(void)
{
	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
			 IRQ_DOVE_UART_2, get_tclk());
}

/*****************************************************************************
 * UART3
 ****************************************************************************/
void __init dove_uart3_init(void)
{
	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
			 IRQ_DOVE_UART_3, get_tclk());
}

/*****************************************************************************
 * SPI0
 ****************************************************************************/
static struct orion_spi_info dove_spi0_data = {
	.tclk		= 0,
};

static struct resource dove_spi0_resources[] = {
	{
		.start	= DOVE_SPI0_PHYS_BASE,
		.end	= DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SPI0,
		.end	= IRQ_DOVE_SPI0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_spi0 = {
	.name		= "orion_spi",
	.id		= 0,
	.resource	= dove_spi0_resources,
	.dev		= {
		.platform_data	= &dove_spi0_data,
	},
	.num_resources	= ARRAY_SIZE(dove_spi0_resources),
};

void __init dove_spi0_init(void)
{
	platform_device_register(&dove_spi0);
}

/*****************************************************************************
 * SPI1
 ****************************************************************************/
static struct orion_spi_info dove_spi1_data = {
	.tclk		= 0,
};

static struct resource dove_spi1_resources[] = {
	{
		.start	= DOVE_SPI1_PHYS_BASE,
		.end	= DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SPI1,
		.end	= IRQ_DOVE_SPI1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_spi1 = {
	.name		= "orion_spi",
	.id		= 1,
	.resource	= dove_spi1_resources,
	.dev		= {
		.platform_data	= &dove_spi1_data,
	},
	.num_resources	= ARRAY_SIZE(dove_spi1_resources),
};

void __init dove_spi1_init(void)
{
	platform_device_register(&dove_spi1);
}

/*****************************************************************************
 * I2C
 ****************************************************************************/
static struct mv64xxx_i2c_pdata dove_i2c_data = {
	.freq_m		= 10, /* assumes 166 MHz TCLK gets 94.3kHz */
	.freq_n		= 3,
	.timeout	= 1000, /* Default timeout of 1 second */
};

static struct resource dove_i2c_resources[] = {
	{
		.name	= "i2c base",
		.start	= DOVE_I2C_PHYS_BASE,
		.end	= DOVE_I2C_PHYS_BASE + 0x20 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "i2c irq",
		.start	= IRQ_DOVE_I2C,
		.end	= IRQ_DOVE_I2C,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_i2c = {
	.name		= MV64XXX_I2C_CTLR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(dove_i2c_resources),
	.resource	= dove_i2c_resources,
	.dev		= {
		.platform_data = &dove_i2c_data,
	},
};

void __init dove_i2c_init(void)
{
	platform_device_register(&dove_i2c);
}

/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init dove_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
}

static int get_tclk(void)
{
	/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
	return 166666667;
}

static void dove_timer_init(void)
{
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_DOVE_BRIDGE, get_tclk());
}

struct sys_timer dove_timer = {
	.init = dove_timer_init,
};

/*****************************************************************************
 * XOR
 ****************************************************************************/
static struct mv_xor_platform_shared_data dove_xor_shared_data = {
	.dram		= &dove_mbus_dram_info,
};

/*****************************************************************************
 * XOR 0
 ****************************************************************************/
static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);

static struct resource dove_xor0_shared_resources[] = {
	{
		.name	= "xor 0 low",
		.start	= DOVE_XOR0_PHYS_BASE,
		.end	= DOVE_XOR0_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "xor 0 high",
		.start	= DOVE_XOR0_HIGH_PHYS_BASE,
		.end	= DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device dove_xor0_shared = {
	.name		= MV_XOR_SHARED_NAME,
	.id		= 0,
	.dev		= {
		.platform_data = &dove_xor_shared_data,
	},
	.num_resources	= ARRAY_SIZE(dove_xor0_shared_resources),
	.resource	= dove_xor0_shared_resources,
};

static struct resource dove_xor00_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_00,
		.end	= IRQ_DOVE_XOR_00,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor00_data = {
	.shared		= &dove_xor0_shared,
	.hw_id		= 0,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor00_channel = {
	.name		= MV_XOR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(dove_xor00_resources),
	.resource	= dove_xor00_resources,
	.dev		= {
		.dma_mask		= &dove_xor0_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor00_data,
	},
};

static struct resource dove_xor01_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_01,
		.end	= IRQ_DOVE_XOR_01,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor01_data = {
	.shared		= &dove_xor0_shared,
	.hw_id		= 1,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor01_channel = {
	.name		= MV_XOR_NAME,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(dove_xor01_resources),
	.resource	= dove_xor01_resources,
	.dev		= {
		.dma_mask		= &dove_xor0_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor01_data,
	},
};

void __init dove_xor0_init(void)
{
	platform_device_register(&dove_xor0_shared);

	/*
	 * two engines can't do memset simultaneously, this limitation
	 * satisfied by removing memset support from one of the engines.
	 */
	dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
	platform_device_register(&dove_xor00_channel);

	dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
	dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
	platform_device_register(&dove_xor01_channel);
}

/*****************************************************************************
 * XOR 1
 ****************************************************************************/
static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);

static struct resource dove_xor1_shared_resources[] = {
	{
		.name	= "xor 0 low",
		.start	= DOVE_XOR1_PHYS_BASE,
		.end	= DOVE_XOR1_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "xor 0 high",
		.start	= DOVE_XOR1_HIGH_PHYS_BASE,
		.end	= DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device dove_xor1_shared = {
	.name		= MV_XOR_SHARED_NAME,
	.id		= 1,
	.dev		= {
		.platform_data = &dove_xor_shared_data,
	},
	.num_resources	= ARRAY_SIZE(dove_xor1_shared_resources),
	.resource	= dove_xor1_shared_resources,
};

static struct resource dove_xor10_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_10,
		.end	= IRQ_DOVE_XOR_10,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor10_data = {
	.shared		= &dove_xor1_shared,
	.hw_id		= 0,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor10_channel = {
	.name		= MV_XOR_NAME,
	.id		= 2,
	.num_resources	= ARRAY_SIZE(dove_xor10_resources),
	.resource	= dove_xor10_resources,
	.dev		= {
		.dma_mask		= &dove_xor1_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor10_data,
	},
};

static struct resource dove_xor11_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_11,
		.end	= IRQ_DOVE_XOR_11,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor11_data = {
	.shared		= &dove_xor1_shared,
	.hw_id		= 1,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor11_channel = {
	.name		= MV_XOR_NAME,
	.id		= 3,
	.num_resources	= ARRAY_SIZE(dove_xor11_resources),
	.resource	= dove_xor11_resources,
	.dev		= {
		.dma_mask		= &dove_xor1_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor11_data,
	},
};

void __init dove_xor1_init(void)
{
	platform_device_register(&dove_xor1_shared);

	/*
	 * two engines can't do memset simultaneously, this limitation
	 * satisfied by removing memset support from one of the engines.
	 */
	dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
	platform_device_register(&dove_xor10_channel);

	dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
	dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
	platform_device_register(&dove_xor11_channel);
}

/*****************************************************************************
 * SDIO
 ****************************************************************************/
static u64 sdio_dmamask = DMA_BIT_MASK(32);

static struct resource dove_sdio0_resources[] = {
	{
		.start	= DOVE_SDIO0_PHYS_BASE,
		.end	= DOVE_SDIO0_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO0,
		.end	= IRQ_DOVE_SDIO0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio0 = {
	.name		= "sdhci-dove",
	.id		= 0,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio0_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio0_resources),
};

void __init dove_sdio0_init(void)
{
	platform_device_register(&dove_sdio0);
}

static struct resource dove_sdio1_resources[] = {
	{
		.start	= DOVE_SDIO1_PHYS_BASE,
		.end	= DOVE_SDIO1_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO1,
		.end	= IRQ_DOVE_SDIO1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio1 = {
	.name		= "sdhci-dove",
	.id		= 1,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio1_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio1_resources),
};

void __init dove_sdio1_init(void)
{
	platform_device_register(&dove_sdio1);
}

void __init dove_init(void)
{
	int tclk;

	tclk = get_tclk();

	printk(KERN_INFO "Dove 88AP510 SoC, ");
	printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);

#ifdef CONFIG_CACHE_TAUROS2
	tauros2_init();
#endif
	dove_setup_cpu_mbus();

	dove_spi0_data.tclk = tclk;
	dove_spi1_data.tclk = tclk;

	/* internal devices that every board has */
	dove_rtc_init();
	dove_xor0_init();
	dove_xor1_init();
}
Commit	Line	Data
edabd38e SB	1	/*
	2	* arch/arm/mach-dove/common.c
	3	*
	4	* Core functions for Marvell Dove 88AP510 System On Chip
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/delay.h>
	13	#include <linux/init.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/pci.h>
	16	#include <linux/serial_8250.h>
	17	#include <linux/clk.h>
	18	#include <linux/mbus.h>
edabd38e SB	19	#include <linux/mv643xx_i2c.h>
edabd38e SB	20	#include <linux/ata_platform.h>
5c602551	21	#include <linux/serial_8250.h>
edabd38e SB	22	#include <linux/spi/orion_spi.h>
	23	#include <linux/gpio.h>
	24	#include <asm/page.h>
	25	#include <asm/setup.h>
	26	#include <asm/timex.h>
573a652f	27	#include <asm/hardware/cache-tauros2.h>
edabd38e SB	28	#include <asm/mach/map.h>
	29	#include <asm/mach/time.h>
	30	#include <asm/mach/pci.h>
	31	#include <mach/dove.h>
	32	#include <mach/bridge-regs.h>
	33	#include <asm/mach/arch.h>
	34	#include <linux/irq.h>
	35	#include <plat/mv_xor.h>
	36	#include <plat/ehci-orion.h>
	37	#include <plat/time.h>
28a2b450	38	#include <plat/common.h>
edabd38e SB	39	#include "common.h"
edabd38e SB	40
28a2b450 AL	41	static int get_tclk(void);
28a2b450 AL	42
edabd38e SB	43	/*****************************************************************************
	44	* I/O Address Mapping
	45	****************************************************************************/
	46	static struct map_desc dove_io_desc[] __initdata = {
	47	{
	48	.virtual = DOVE_SB_REGS_VIRT_BASE,
	49	.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
	50	.length = DOVE_SB_REGS_SIZE,
	51	.type = MT_DEVICE,
	52	}, {
	53	.virtual = DOVE_NB_REGS_VIRT_BASE,
	54	.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
	55	.length = DOVE_NB_REGS_SIZE,
	56	.type = MT_DEVICE,
	57	}, {
	58	.virtual = DOVE_PCIE0_IO_VIRT_BASE,
	59	.pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
	60	.length = DOVE_PCIE0_IO_SIZE,
	61	.type = MT_DEVICE,
	62	}, {
	63	.virtual = DOVE_PCIE1_IO_VIRT_BASE,
	64	.pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
	65	.length = DOVE_PCIE1_IO_SIZE,
	66	.type = MT_DEVICE,
	67	},
	68	};
	69
	70	void __init dove_map_io(void)
	71	{
	72	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
	73	}
	74
	75	/*****************************************************************************
	76	* EHCI
	77	****************************************************************************/
	78	static struct orion_ehci_data dove_ehci_data = {
	79	.dram = &dove_mbus_dram_info,
	80	.phy_version = EHCI_PHY_NA,
	81	};
	82
	83	static u64 ehci_dmamask = DMA_BIT_MASK(32);
	84
	85	/*****************************************************************************
	86	* EHCI0
	87	****************************************************************************/
	88	static struct resource dove_ehci0_resources[] = {
	89	{
	90	.start = DOVE_USB0_PHYS_BASE,
	91	.end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
	92	.flags = IORESOURCE_MEM,
	93	}, {
	94	.start = IRQ_DOVE_USB0,
	95	.end = IRQ_DOVE_USB0,
	96	.flags = IORESOURCE_IRQ,
	97	},
	98	};
	99
	100	static struct platform_device dove_ehci0 = {
	101	.name = "orion-ehci",
	102	.id = 0,
	103	.dev = {
	104	.dma_mask = &ehci_dmamask,
	105	.coherent_dma_mask = DMA_BIT_MASK(32),
	106	.platform_data = &dove_ehci_data,
107	},
108	.resource = dove_ehci0_resources,
109	.num_resources = ARRAY_SIZE(dove_ehci0_resources),
110	};
111
112	void __init dove_ehci0_init(void)
113	{
114	platform_device_register(&dove_ehci0);
115	}
116
117	/*****************************************************************************
118	* EHCI1
119	****************************************************************************/
120	static struct resource dove_ehci1_resources[] = {
121	{
122	.start = DOVE_USB1_PHYS_BASE,
123	.end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
124	.flags = IORESOURCE_MEM,
125	}, {
126	.start = IRQ_DOVE_USB1,
127	.end = IRQ_DOVE_USB1,
128	.flags = IORESOURCE_IRQ,
129	},
130	};
131
132	static struct platform_device dove_ehci1 = {
133	.name = "orion-ehci",
134	.id = 1,
135	.dev = {
136	.dma_mask = &ehci_dmamask,
137	.coherent_dma_mask = DMA_BIT_MASK(32),
138	.platform_data = &dove_ehci_data,
139	},
140	.resource = dove_ehci1_resources,
141	.num_resources = ARRAY_SIZE(dove_ehci1_resources),
142	};
143
144	void __init dove_ehci1_init(void)
145	{
146	platform_device_register(&dove_ehci1);
147	}
148
149	/*****************************************************************************
150	* GE00
151	****************************************************************************/
edabd38e SB	152	void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
edabd38e SB	153	{
7e3819d8 AL	154	orion_ge00_init(eth_data, &dove_mbus_dram_info,
	155	DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
	156	0, get_tclk());
edabd38e SB	157	}
	158
	159	/*****************************************************************************
	160	* SoC RTC
	161	****************************************************************************/
edabd38e SB	162	void __init dove_rtc_init(void)
edabd38e SB	163	{
f6eaccb3	164	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
edabd38e SB	165	}
	166
	167	/*****************************************************************************
	168	* SATA
	169	****************************************************************************/
	170	static struct resource dove_sata_resources[] = {
	171	{
	172	.name = "sata base",
	173	.start = DOVE_SATA_PHYS_BASE,
	174	.end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
	175	.flags = IORESOURCE_MEM,
	176	}, {
	177	.name = "sata irq",
	178	.start = IRQ_DOVE_SATA,
	179	.end = IRQ_DOVE_SATA,
	180	.flags = IORESOURCE_IRQ,
	181	},
	182	};
	183
	184	static struct platform_device dove_sata = {
	185	.name = "sata_mv",
	186	.id = 0,
	187	.dev = {
	188	.coherent_dma_mask = DMA_BIT_MASK(32),
	189	},
	190	.num_resources = ARRAY_SIZE(dove_sata_resources),
	191	.resource = dove_sata_resources,
	192	};
	193
	194	void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
	195	{
	196	sata_data->dram = &dove_mbus_dram_info;
	197	dove_sata.dev.platform_data = sata_data;
	198	platform_device_register(&dove_sata);
	199	}
	200
	201	/*****************************************************************************
	202	* UART0
	203	****************************************************************************/
edabd38e SB	204	void __init dove_uart0_init(void)
edabd38e SB	205	{
28a2b450 AL	206	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
28a2b450 AL	207	IRQ_DOVE_UART_0, get_tclk());
edabd38e SB	208	}
	209
	210	/*****************************************************************************
	211	* UART1
	212	****************************************************************************/
edabd38e SB	213	void __init dove_uart1_init(void)
edabd38e SB	214	{
28a2b450 AL	215	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
28a2b450 AL	216	IRQ_DOVE_UART_1, get_tclk());
edabd38e SB	217	}
	218
	219	/*****************************************************************************
	220	* UART2
	221	****************************************************************************/
edabd38e SB	222	void __init dove_uart2_init(void)
edabd38e SB	223	{
28a2b450 AL	224	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
28a2b450 AL	225	IRQ_DOVE_UART_2, get_tclk());
edabd38e SB	226	}
	227
	228	/*****************************************************************************
	229	* UART3
	230	****************************************************************************/
edabd38e SB	231	void __init dove_uart3_init(void)
edabd38e SB	232	{
28a2b450 AL	233	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
28a2b450 AL	234	IRQ_DOVE_UART_3, get_tclk());
edabd38e SB	235	}
	236
	237	/*****************************************************************************
	238	* SPI0
	239	****************************************************************************/
	240	static struct orion_spi_info dove_spi0_data = {
	241	.tclk = 0,
	242	};
	243
	244	static struct resource dove_spi0_resources[] = {
	245	{
	246	.start = DOVE_SPI0_PHYS_BASE,
	247	.end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
	248	.flags = IORESOURCE_MEM,
	249	}, {
	250	.start = IRQ_DOVE_SPI0,
	251	.end = IRQ_DOVE_SPI0,
	252	.flags = IORESOURCE_IRQ,
	253	},
	254	};
	255
	256	static struct platform_device dove_spi0 = {
	257	.name = "orion_spi",
	258	.id = 0,
	259	.resource = dove_spi0_resources,
	260	.dev = {
	261	.platform_data = &dove_spi0_data,
	262	},
	263	.num_resources = ARRAY_SIZE(dove_spi0_resources),
	264	};
	265
	266	void __init dove_spi0_init(void)
	267	{
	268	platform_device_register(&dove_spi0);
	269	}
	270
	271	/*****************************************************************************
	272	* SPI1
	273	****************************************************************************/
	274	static struct orion_spi_info dove_spi1_data = {
	275	.tclk = 0,
	276	};
	277
	278	static struct resource dove_spi1_resources[] = {
	279	{
	280	.start = DOVE_SPI1_PHYS_BASE,
	281	.end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
	282	.flags = IORESOURCE_MEM,
	283	}, {
	284	.start = IRQ_DOVE_SPI1,
	285	.end = IRQ_DOVE_SPI1,
	286	.flags = IORESOURCE_IRQ,
	287	},
	288	};
	289
	290	static struct platform_device dove_spi1 = {
	291	.name = "orion_spi",
	292	.id = 1,
	293	.resource = dove_spi1_resources,
	294	.dev = {
	295	.platform_data = &dove_spi1_data,
	296	},
	297	.num_resources = ARRAY_SIZE(dove_spi1_resources),
	298	};
299
300	void __init dove_spi1_init(void)
301	{
302	platform_device_register(&dove_spi1);
303	}
304
305	/*****************************************************************************
306	* I2C
307	****************************************************************************/
308	static struct mv64xxx_i2c_pdata dove_i2c_data = {
309	.freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
310	.freq_n = 3,
311	.timeout = 1000, /* Default timeout of 1 second */
312	};
313
314	static struct resource dove_i2c_resources[] = {
315	{
316	.name = "i2c base",
317	.start = DOVE_I2C_PHYS_BASE,
318	.end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
319	.flags = IORESOURCE_MEM,
320	}, {
321	.name = "i2c irq",
322	.start = IRQ_DOVE_I2C,
323	.end = IRQ_DOVE_I2C,
324	.flags = IORESOURCE_IRQ,
325	},
326	};
327
328	static struct platform_device dove_i2c = {
329	.name = MV64XXX_I2C_CTLR_NAME,
330	.id = 0,
331	.num_resources = ARRAY_SIZE(dove_i2c_resources),
332	.resource = dove_i2c_resources,
333	.dev = {
334	.platform_data = &dove_i2c_data,
335	},
336	};
337
338	void __init dove_i2c_init(void)
339	{
340	platform_device_register(&dove_i2c);
341	}
342
343	/*****************************************************************************
344	* Time handling
345	****************************************************************************/
4ee1f6b5 LB	346	void __init dove_init_early(void)
	347	{
	348	orion_time_set_base(TIMER_VIRT_BASE);
	349	}
	350
edabd38e SB	351	static int get_tclk(void)
	352	{
	353	/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
	354	return 166666667;
	355	}
	356
	357	static void dove_timer_init(void)
	358	{
4ee1f6b5 LB	359	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
4ee1f6b5 LB	360	IRQ_DOVE_BRIDGE, get_tclk());
edabd38e SB	361	}
	362
	363	struct sys_timer dove_timer = {
	364	.init = dove_timer_init,
	365	};
	366
	367	/*****************************************************************************
	368	* XOR
	369	****************************************************************************/
	370	static struct mv_xor_platform_shared_data dove_xor_shared_data = {
	371	.dram = &dove_mbus_dram_info,
	372	};
	373
	374	/*****************************************************************************
	375	* XOR 0
	376	****************************************************************************/
	377	static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
	378
	379	static struct resource dove_xor0_shared_resources[] = {
	380	{
	381	.name = "xor 0 low",
	382	.start = DOVE_XOR0_PHYS_BASE,
	383	.end = DOVE_XOR0_PHYS_BASE + 0xff,
	384	.flags = IORESOURCE_MEM,
	385	}, {
	386	.name = "xor 0 high",
	387	.start = DOVE_XOR0_HIGH_PHYS_BASE,
	388	.end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
	389	.flags = IORESOURCE_MEM,
	390	},
	391	};
	392
	393	static struct platform_device dove_xor0_shared = {
	394	.name = MV_XOR_SHARED_NAME,
	395	.id = 0,
	396	.dev = {
	397	.platform_data = &dove_xor_shared_data,
	398	},
	399	.num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
	400	.resource = dove_xor0_shared_resources,
	401	};
	402
	403	static struct resource dove_xor00_resources[] = {
	404	[0] = {
	405	.start = IRQ_DOVE_XOR_00,
	406	.end = IRQ_DOVE_XOR_00,
	407	.flags = IORESOURCE_IRQ,
	408	},
	409	};
	410
	411	static struct mv_xor_platform_data dove_xor00_data = {
	412	.shared = &dove_xor0_shared,
	413	.hw_id = 0,
	414	.pool_size = PAGE_SIZE,
	415	};
	416
	417	static struct platform_device dove_xor00_channel = {
	418	.name = MV_XOR_NAME,
	419	.id = 0,
	420	.num_resources = ARRAY_SIZE(dove_xor00_resources),
	421	.resource = dove_xor00_resources,
	422	.dev = {
	423	.dma_mask = &dove_xor0_dmamask,
	424	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	425	.platform_data = &dove_xor00_data,
edabd38e SB	426	},
	427	};
	428
	429	static struct resource dove_xor01_resources[] = {
	430	[0] = {
	431	.start = IRQ_DOVE_XOR_01,
	432	.end = IRQ_DOVE_XOR_01,
	433	.flags = IORESOURCE_IRQ,
	434	},
	435	};
	436
	437	static struct mv_xor_platform_data dove_xor01_data = {
	438	.shared = &dove_xor0_shared,
	439	.hw_id = 1,
	440	.pool_size = PAGE_SIZE,
	441	};
	442
	443	static struct platform_device dove_xor01_channel = {
	444	.name = MV_XOR_NAME,
	445	.id = 1,
	446	.num_resources = ARRAY_SIZE(dove_xor01_resources),
	447	.resource = dove_xor01_resources,
	448	.dev = {
	449	.dma_mask = &dove_xor0_dmamask,
	450	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	451	.platform_data = &dove_xor01_data,
edabd38e SB	452	},
	453	};
	454
	455	void __init dove_xor0_init(void)
	456	{
	457	platform_device_register(&dove_xor0_shared);
	458
	459	/*
	460	* two engines can't do memset simultaneously, this limitation
	461	* satisfied by removing memset support from one of the engines.
	462	*/
	463	dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
	464	dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
	465	platform_device_register(&dove_xor00_channel);
	466
	467	dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
	468	dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
	469	dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
	470	platform_device_register(&dove_xor01_channel);
	471	}
	472
	473	/*****************************************************************************
	474	* XOR 1
	475	****************************************************************************/
	476	static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
	477
	478	static struct resource dove_xor1_shared_resources[] = {
	479	{
	480	.name = "xor 0 low",
	481	.start = DOVE_XOR1_PHYS_BASE,
	482	.end = DOVE_XOR1_PHYS_BASE + 0xff,
	483	.flags = IORESOURCE_MEM,
	484	}, {
	485	.name = "xor 0 high",
	486	.start = DOVE_XOR1_HIGH_PHYS_BASE,
	487	.end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
	488	.flags = IORESOURCE_MEM,
	489	},
	490	};
	491
	492	static struct platform_device dove_xor1_shared = {
	493	.name = MV_XOR_SHARED_NAME,
	494	.id = 1,
	495	.dev = {
	496	.platform_data = &dove_xor_shared_data,
	497	},
	498	.num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
	499	.resource = dove_xor1_shared_resources,
	500	};
	501
	502	static struct resource dove_xor10_resources[] = {
	503	[0] = {
	504	.start = IRQ_DOVE_XOR_10,
	505	.end = IRQ_DOVE_XOR_10,
	506	.flags = IORESOURCE_IRQ,
	507	},
	508	};
	509
	510	static struct mv_xor_platform_data dove_xor10_data = {
	511	.shared = &dove_xor1_shared,
	512	.hw_id = 0,
	513	.pool_size = PAGE_SIZE,
	514	};
	515
516	static struct platform_device dove_xor10_channel = {
517	.name = MV_XOR_NAME,
518	.id = 2,
519	.num_resources = ARRAY_SIZE(dove_xor10_resources),
520	.resource = dove_xor10_resources,
521	.dev = {
522	.dma_mask = &dove_xor1_dmamask,
523	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	524	.platform_data = &dove_xor10_data,
edabd38e SB	525	},
	526	};
	527
	528	static struct resource dove_xor11_resources[] = {
	529	[0] = {
	530	.start = IRQ_DOVE_XOR_11,
	531	.end = IRQ_DOVE_XOR_11,
	532	.flags = IORESOURCE_IRQ,
	533	},
	534	};
	535
	536	static struct mv_xor_platform_data dove_xor11_data = {
	537	.shared = &dove_xor1_shared,
	538	.hw_id = 1,
	539	.pool_size = PAGE_SIZE,
	540	};
	541
	542	static struct platform_device dove_xor11_channel = {
	543	.name = MV_XOR_NAME,
	544	.id = 3,
	545	.num_resources = ARRAY_SIZE(dove_xor11_resources),
	546	.resource = dove_xor11_resources,
	547	.dev = {
	548	.dma_mask = &dove_xor1_dmamask,
	549	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	550	.platform_data = &dove_xor11_data,
edabd38e SB	551	},
	552	};
	553
	554	void __init dove_xor1_init(void)
	555	{
	556	platform_device_register(&dove_xor1_shared);
	557
	558	/*
	559	* two engines can't do memset simultaneously, this limitation
	560	* satisfied by removing memset support from one of the engines.
	561	*/
	562	dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
	563	dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
	564	platform_device_register(&dove_xor10_channel);
	565
	566	dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
	567	dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
	568	dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
	569	platform_device_register(&dove_xor11_channel);
	570	}
	571
16bc90af SB	572	/*****************************************************************************
	573	* SDIO
	574	****************************************************************************/
	575	static u64 sdio_dmamask = DMA_BIT_MASK(32);
	576
	577	static struct resource dove_sdio0_resources[] = {
	578	{
	579	.start = DOVE_SDIO0_PHYS_BASE,
	580	.end = DOVE_SDIO0_PHYS_BASE + 0xff,
	581	.flags = IORESOURCE_MEM,
	582	}, {
	583	.start = IRQ_DOVE_SDIO0,
	584	.end = IRQ_DOVE_SDIO0,
	585	.flags = IORESOURCE_IRQ,
	586	},
	587	};
	588
	589	static struct platform_device dove_sdio0 = {
930e2fe7	590	.name = "sdhci-dove",
16bc90af SB	591	.id = 0,
	592	.dev = {
	593	.dma_mask = &sdio_dmamask,
	594	.coherent_dma_mask = DMA_BIT_MASK(32),
	595	},
	596	.resource = dove_sdio0_resources,
	597	.num_resources = ARRAY_SIZE(dove_sdio0_resources),
	598	};
	599
	600	void __init dove_sdio0_init(void)
	601	{
	602	platform_device_register(&dove_sdio0);
	603	}
	604
	605	static struct resource dove_sdio1_resources[] = {
	606	{
	607	.start = DOVE_SDIO1_PHYS_BASE,
	608	.end = DOVE_SDIO1_PHYS_BASE + 0xff,
	609	.flags = IORESOURCE_MEM,
	610	}, {
	611	.start = IRQ_DOVE_SDIO1,
	612	.end = IRQ_DOVE_SDIO1,
	613	.flags = IORESOURCE_IRQ,
	614	},
	615	};
	616
	617	static struct platform_device dove_sdio1 = {
930e2fe7	618	.name = "sdhci-dove",
16bc90af SB	619	.id = 1,
	620	.dev = {
	621	.dma_mask = &sdio_dmamask,
	622	.coherent_dma_mask = DMA_BIT_MASK(32),
	623	},
	624	.resource = dove_sdio1_resources,
	625	.num_resources = ARRAY_SIZE(dove_sdio1_resources),
	626	};
	627
	628	void __init dove_sdio1_init(void)
	629	{
	630	platform_device_register(&dove_sdio1);
	631	}
	632
edabd38e SB	633	void __init dove_init(void)
	634	{
	635	int tclk;
	636
	637	tclk = get_tclk();
	638
	639	printk(KERN_INFO "Dove 88AP510 SoC, ");
	640	printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
	641
573a652f LB	642	#ifdef CONFIG_CACHE_TAUROS2
	643	tauros2_init();
	644	#endif
edabd38e SB	645	dove_setup_cpu_mbus();
edabd38e SB	646
edabd38e SB	647	dove_spi0_data.tclk = tclk;
	648	dove_spi1_data.tclk = tclk;
	649
	650	/* internal devices that every board has */
	651	dove_rtc_init();
	652	dove_xor0_init();
	653	dove_xor1_init();
	654	}