[linux-2.6-block.git] / arch / arm / mach-dove / common.c

/*
 * arch/arm/mach-dove/common.c
 *
 * Core functions for Marvell Dove 88AP510 System On Chip
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/clk-provider.h>
#include <linux/ata_platform.h>
#include <linux/gpio.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/pci.h>
#include <mach/dove.h>
#include <mach/bridge-regs.h>
#include <asm/mach/arch.h>
#include <linux/irq.h>
#include <plat/time.h>
#include <plat/ehci-orion.h>
#include <plat/common.h>
#include <plat/addr-map.h>
#include "common.h"

static int get_tclk(void);

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc dove_io_desc[] __initdata = {
	{
		.virtual	= DOVE_SB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
		.length		= DOVE_SB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_NB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
		.length		= DOVE_NB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_PCIE0_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
		.length		= DOVE_PCIE0_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_PCIE1_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
		.length		= DOVE_PCIE1_IO_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init dove_map_io(void)
{
	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
}

/*****************************************************************************
 * CLK tree
 ****************************************************************************/
static struct clk *tclk;

static void __init clk_init(void)
{
	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
				       get_tclk());
}

/*****************************************************************************
 * EHCI0
 ****************************************************************************/
void __init dove_ehci0_init(void)
{
	orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
}

/*****************************************************************************
 * EHCI1
 ****************************************************************************/
void __init dove_ehci1_init(void)
{
	orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
}

/*****************************************************************************
 * GE00
 ****************************************************************************/
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge00_init(eth_data,
			DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
			0, get_tclk());
}

/*****************************************************************************
 * SoC RTC
 ****************************************************************************/
void __init dove_rtc_init(void)
{
	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}

/*****************************************************************************
 * SATA
 ****************************************************************************/
void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
	orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);

}

/*****************************************************************************
 * UART0
 ****************************************************************************/
void __init dove_uart0_init(void)
{
	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
			 IRQ_DOVE_UART_0, get_tclk());
}

/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init dove_uart1_init(void)
{
	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
			 IRQ_DOVE_UART_1, get_tclk());
}

/*****************************************************************************
 * UART2
 ****************************************************************************/
void __init dove_uart2_init(void)
{
	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
			 IRQ_DOVE_UART_2, get_tclk());
}

/*****************************************************************************
 * UART3
 ****************************************************************************/
void __init dove_uart3_init(void)
{
	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
			 IRQ_DOVE_UART_3, get_tclk());
}

/*****************************************************************************
 * SPI
 ****************************************************************************/
void __init dove_spi0_init(void)
{
	orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
}

void __init dove_spi1_init(void)
{
	orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
}

/*****************************************************************************
 * I2C
 ****************************************************************************/
void __init dove_i2c_init(void)
{
	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
}

/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init dove_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
}

static int get_tclk(void)
{
	/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
	return 166666667;
}

static void dove_timer_init(void)
{
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_DOVE_BRIDGE, get_tclk());
}

struct sys_timer dove_timer = {
	.init = dove_timer_init,
};

/*****************************************************************************
 * XOR 0
 ****************************************************************************/
void __init dove_xor0_init(void)
{
	orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
			IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
}

/*****************************************************************************
 * XOR 1
 ****************************************************************************/
void __init dove_xor1_init(void)
{
	orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
			IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
}

/*****************************************************************************
 * SDIO
 ****************************************************************************/
static u64 sdio_dmamask = DMA_BIT_MASK(32);

static struct resource dove_sdio0_resources[] = {
	{
		.start	= DOVE_SDIO0_PHYS_BASE,
		.end	= DOVE_SDIO0_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO0,
		.end	= IRQ_DOVE_SDIO0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio0 = {
	.name		= "sdhci-dove",
	.id		= 0,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio0_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio0_resources),
};

void __init dove_sdio0_init(void)
{
	platform_device_register(&dove_sdio0);
}

static struct resource dove_sdio1_resources[] = {
	{
		.start	= DOVE_SDIO1_PHYS_BASE,
		.end	= DOVE_SDIO1_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO1,
		.end	= IRQ_DOVE_SDIO1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio1 = {
	.name		= "sdhci-dove",
	.id		= 1,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio1_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio1_resources),
};

void __init dove_sdio1_init(void)
{
	platform_device_register(&dove_sdio1);
}

void __init dove_init(void)
{
	printk(KERN_INFO "Dove 88AP510 SoC, ");
	printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);

#ifdef CONFIG_CACHE_TAUROS2
	tauros2_init();
#endif
	dove_setup_cpu_mbus();

	/* Setup root of clk tree */
	clk_init();

	/* internal devices that every board has */
	dove_rtc_init();
	dove_xor0_init();
	dove_xor1_init();
}

void dove_restart(char mode, const char *cmd)
{
	/*
	 * Enable soft reset to assert RSTOUTn.
	 */
	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);

	/*
	 * Assert soft reset.
	 */
	writel(SOFT_RESET, SYSTEM_SOFT_RESET);

	while (1)
		;
}
Commit	Line	Data
edabd38e SB	1	/*
	2	* arch/arm/mach-dove/common.c
	3	*
	4	* Core functions for Marvell Dove 88AP510 System On Chip
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/delay.h>
	13	#include <linux/init.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/pci.h>
2f129bf4	16	#include <linux/clk-provider.h>
edabd38e	17	#include <linux/ata_platform.h>
edabd38e SB	18	#include <linux/gpio.h>
	19	#include <asm/page.h>
	20	#include <asm/setup.h>
	21	#include <asm/timex.h>
573a652f	22	#include <asm/hardware/cache-tauros2.h>
edabd38e SB	23	#include <asm/mach/map.h>
	24	#include <asm/mach/time.h>
	25	#include <asm/mach/pci.h>
	26	#include <mach/dove.h>
	27	#include <mach/bridge-regs.h>
	28	#include <asm/mach/arch.h>
	29	#include <linux/irq.h>
edabd38e	30	#include <plat/time.h>
72053353	31	#include <plat/ehci-orion.h>
28a2b450	32	#include <plat/common.h>
45173d5e	33	#include <plat/addr-map.h>
edabd38e SB	34	#include "common.h"
edabd38e SB	35
28a2b450 AL	36	static int get_tclk(void);
28a2b450 AL	37
edabd38e SB	38	/*****************************************************************************
	39	* I/O Address Mapping
	40	****************************************************************************/
	41	static struct map_desc dove_io_desc[] __initdata = {
	42	{
	43	.virtual = DOVE_SB_REGS_VIRT_BASE,
	44	.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
	45	.length = DOVE_SB_REGS_SIZE,
	46	.type = MT_DEVICE,
	47	}, {
	48	.virtual = DOVE_NB_REGS_VIRT_BASE,
	49	.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
	50	.length = DOVE_NB_REGS_SIZE,
	51	.type = MT_DEVICE,
	52	}, {
	53	.virtual = DOVE_PCIE0_IO_VIRT_BASE,
	54	.pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
	55	.length = DOVE_PCIE0_IO_SIZE,
	56	.type = MT_DEVICE,
	57	}, {
	58	.virtual = DOVE_PCIE1_IO_VIRT_BASE,
	59	.pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
	60	.length = DOVE_PCIE1_IO_SIZE,
	61	.type = MT_DEVICE,
	62	},
	63	};
	64
	65	void __init dove_map_io(void)
	66	{
	67	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
	68	}
	69
2f129bf4 AL	70	/*****************************************************************************
	71	* CLK tree
	72	****************************************************************************/
	73	static struct clk *tclk;
	74
	75	static void __init clk_init(void)
	76	{
	77	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
	78	get_tclk());
	79	}
	80
edabd38e SB	81	/*****************************************************************************
	82	* EHCI0
	83	****************************************************************************/
edabd38e SB	84	void __init dove_ehci0_init(void)
edabd38e SB	85	{
72053353	86	orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
edabd38e SB	87	}
	88
	89	/*****************************************************************************
	90	* EHCI1
	91	****************************************************************************/
edabd38e SB	92	void __init dove_ehci1_init(void)
edabd38e SB	93	{
db33f4de	94	orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
edabd38e SB	95	}
	96
	97	/*****************************************************************************
	98	* GE00
	99	****************************************************************************/
edabd38e SB	100	void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
edabd38e SB	101	{
db33f4de	102	orion_ge00_init(eth_data,
7e3819d8 AL	103	DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
7e3819d8 AL	104	0, get_tclk());
edabd38e SB	105	}
	106
	107	/*****************************************************************************
	108	* SoC RTC
	109	****************************************************************************/
edabd38e SB	110	void __init dove_rtc_init(void)
edabd38e SB	111	{
f6eaccb3	112	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
edabd38e SB	113	}
	114
	115	/*****************************************************************************
	116	* SATA
	117	****************************************************************************/
edabd38e SB	118	void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
edabd38e SB	119	{
db33f4de	120	orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
9e613f8a	121
edabd38e SB	122	}
	123
	124	/*****************************************************************************
	125	* UART0
	126	****************************************************************************/
edabd38e SB	127	void __init dove_uart0_init(void)
edabd38e SB	128	{
28a2b450 AL	129	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
28a2b450 AL	130	IRQ_DOVE_UART_0, get_tclk());
edabd38e SB	131	}
	132
	133	/*****************************************************************************
	134	* UART1
	135	****************************************************************************/
edabd38e SB	136	void __init dove_uart1_init(void)
edabd38e SB	137	{
28a2b450 AL	138	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
28a2b450 AL	139	IRQ_DOVE_UART_1, get_tclk());
edabd38e SB	140	}
	141
	142	/*****************************************************************************
	143	* UART2
	144	****************************************************************************/
edabd38e SB	145	void __init dove_uart2_init(void)
edabd38e SB	146	{
28a2b450 AL	147	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
28a2b450 AL	148	IRQ_DOVE_UART_2, get_tclk());
edabd38e SB	149	}
	150
	151	/*****************************************************************************
	152	* UART3
	153	****************************************************************************/
edabd38e SB	154	void __init dove_uart3_init(void)
edabd38e SB	155	{
28a2b450 AL	156	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
28a2b450 AL	157	IRQ_DOVE_UART_3, get_tclk());
edabd38e SB	158	}
	159
	160	/*****************************************************************************
980f9f60	161	* SPI
edabd38e	162	****************************************************************************/
edabd38e SB	163	void __init dove_spi0_init(void)
edabd38e SB	164	{
980f9f60	165	orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
edabd38e SB	166	}
edabd38e SB	167
edabd38e SB	168	void __init dove_spi1_init(void)
edabd38e SB	169	{
72cc2056	170	orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
edabd38e SB	171	}
	172
	173	/*****************************************************************************
	174	* I2C
	175	****************************************************************************/
edabd38e SB	176	void __init dove_i2c_init(void)
edabd38e SB	177	{
aac7ffa3	178	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
edabd38e SB	179	}
	180
	181	/*****************************************************************************
	182	* Time handling
	183	****************************************************************************/
4ee1f6b5 LB	184	void __init dove_init_early(void)
	185	{
	186	orion_time_set_base(TIMER_VIRT_BASE);
	187	}
	188
edabd38e SB	189	static int get_tclk(void)
	190	{
	191	/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
	192	return 166666667;
	193	}
	194
	195	static void dove_timer_init(void)
	196	{
4ee1f6b5 LB	197	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
4ee1f6b5 LB	198	IRQ_DOVE_BRIDGE, get_tclk());
edabd38e SB	199	}
	200
	201	struct sys_timer dove_timer = {
	202	.init = dove_timer_init,
	203	};
	204
edabd38e SB	205	/*****************************************************************************
	206	* XOR 0
	207	****************************************************************************/
edabd38e SB	208	void __init dove_xor0_init(void)
edabd38e SB	209	{
db33f4de	210	orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
ee962723	211	IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
edabd38e SB	212	}
	213
	214	/*****************************************************************************
	215	* XOR 1
	216	****************************************************************************/
edabd38e SB	217	void __init dove_xor1_init(void)
edabd38e SB	218	{
ee962723 AL	219	orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
ee962723 AL	220	IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
edabd38e SB	221	}
edabd38e SB	222
16bc90af SB	223	/*****************************************************************************
	224	* SDIO
	225	****************************************************************************/
	226	static u64 sdio_dmamask = DMA_BIT_MASK(32);
	227
	228	static struct resource dove_sdio0_resources[] = {
	229	{
	230	.start = DOVE_SDIO0_PHYS_BASE,
	231	.end = DOVE_SDIO0_PHYS_BASE + 0xff,
	232	.flags = IORESOURCE_MEM,
	233	}, {
	234	.start = IRQ_DOVE_SDIO0,
	235	.end = IRQ_DOVE_SDIO0,
	236	.flags = IORESOURCE_IRQ,
	237	},
	238	};
	239
	240	static struct platform_device dove_sdio0 = {
930e2fe7	241	.name = "sdhci-dove",
16bc90af SB	242	.id = 0,
	243	.dev = {
	244	.dma_mask = &sdio_dmamask,
	245	.coherent_dma_mask = DMA_BIT_MASK(32),
	246	},
	247	.resource = dove_sdio0_resources,
	248	.num_resources = ARRAY_SIZE(dove_sdio0_resources),
	249	};
	250
	251	void __init dove_sdio0_init(void)
	252	{
	253	platform_device_register(&dove_sdio0);
	254	}
	255
	256	static struct resource dove_sdio1_resources[] = {
	257	{
	258	.start = DOVE_SDIO1_PHYS_BASE,
	259	.end = DOVE_SDIO1_PHYS_BASE + 0xff,
	260	.flags = IORESOURCE_MEM,
	261	}, {
	262	.start = IRQ_DOVE_SDIO1,
	263	.end = IRQ_DOVE_SDIO1,
	264	.flags = IORESOURCE_IRQ,
	265	},
	266	};
	267
	268	static struct platform_device dove_sdio1 = {
930e2fe7	269	.name = "sdhci-dove",
16bc90af SB	270	.id = 1,
	271	.dev = {
	272	.dma_mask = &sdio_dmamask,
	273	.coherent_dma_mask = DMA_BIT_MASK(32),
	274	},
	275	.resource = dove_sdio1_resources,
	276	.num_resources = ARRAY_SIZE(dove_sdio1_resources),
	277	};
	278
	279	void __init dove_sdio1_init(void)
	280	{
	281	platform_device_register(&dove_sdio1);
	282	}
	283
edabd38e SB	284	void __init dove_init(void)
edabd38e SB	285	{
edabd38e	286	printk(KERN_INFO "Dove 88AP510 SoC, ");
2f129bf4	287	printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
edabd38e	288
573a652f LB	289	#ifdef CONFIG_CACHE_TAUROS2
	290	tauros2_init();
	291	#endif
edabd38e SB	292	dove_setup_cpu_mbus();
edabd38e SB	293
2f129bf4 AL	294	/* Setup root of clk tree */
	295	clk_init();
	296
edabd38e SB	297	/* internal devices that every board has */
	298	dove_rtc_init();
	299	dove_xor0_init();
	300	dove_xor1_init();
	301	}
6ca6ff97 RK	302
	303	void dove_restart(char mode, const char *cmd)
	304	{
	305	/*
	306	* Enable soft reset to assert RSTOUTn.
	307	*/
	308	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
	309
	310	/*
	311	* Assert soft reset.
	312	*/
	313	writel(SOFT_RESET, SYSTEM_SOFT_RESET);
	314
	315	while (1)
	316	;
	317	}