Commit | Line | Data |
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edabd38e SB |
1 | /* |
2 | * arch/arm/mach-dove/common.c | |
3 | * | |
4 | * Core functions for Marvell Dove 88AP510 System On Chip | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/pci.h> | |
2f129bf4 | 16 | #include <linux/clk-provider.h> |
edabd38e | 17 | #include <linux/ata_platform.h> |
edabd38e SB |
18 | #include <linux/gpio.h> |
19 | #include <asm/page.h> | |
20 | #include <asm/setup.h> | |
21 | #include <asm/timex.h> | |
573a652f | 22 | #include <asm/hardware/cache-tauros2.h> |
edabd38e SB |
23 | #include <asm/mach/map.h> |
24 | #include <asm/mach/time.h> | |
25 | #include <asm/mach/pci.h> | |
26 | #include <mach/dove.h> | |
27 | #include <mach/bridge-regs.h> | |
28 | #include <asm/mach/arch.h> | |
29 | #include <linux/irq.h> | |
edabd38e | 30 | #include <plat/time.h> |
72053353 | 31 | #include <plat/ehci-orion.h> |
28a2b450 | 32 | #include <plat/common.h> |
45173d5e | 33 | #include <plat/addr-map.h> |
edabd38e SB |
34 | #include "common.h" |
35 | ||
28a2b450 AL |
36 | static int get_tclk(void); |
37 | ||
edabd38e SB |
38 | /***************************************************************************** |
39 | * I/O Address Mapping | |
40 | ****************************************************************************/ | |
41 | static struct map_desc dove_io_desc[] __initdata = { | |
42 | { | |
43 | .virtual = DOVE_SB_REGS_VIRT_BASE, | |
44 | .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), | |
45 | .length = DOVE_SB_REGS_SIZE, | |
46 | .type = MT_DEVICE, | |
47 | }, { | |
48 | .virtual = DOVE_NB_REGS_VIRT_BASE, | |
49 | .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), | |
50 | .length = DOVE_NB_REGS_SIZE, | |
51 | .type = MT_DEVICE, | |
52 | }, { | |
53 | .virtual = DOVE_PCIE0_IO_VIRT_BASE, | |
54 | .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), | |
55 | .length = DOVE_PCIE0_IO_SIZE, | |
56 | .type = MT_DEVICE, | |
57 | }, { | |
58 | .virtual = DOVE_PCIE1_IO_VIRT_BASE, | |
59 | .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), | |
60 | .length = DOVE_PCIE1_IO_SIZE, | |
61 | .type = MT_DEVICE, | |
62 | }, | |
63 | }; | |
64 | ||
65 | void __init dove_map_io(void) | |
66 | { | |
67 | iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); | |
68 | } | |
69 | ||
2f129bf4 AL |
70 | /***************************************************************************** |
71 | * CLK tree | |
72 | ****************************************************************************/ | |
73 | static struct clk *tclk; | |
74 | ||
75 | static void __init clk_init(void) | |
76 | { | |
77 | tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, | |
78 | get_tclk()); | |
4574b886 AL |
79 | |
80 | orion_clkdev_init(tclk); | |
2f129bf4 AL |
81 | } |
82 | ||
edabd38e SB |
83 | /***************************************************************************** |
84 | * EHCI0 | |
85 | ****************************************************************************/ | |
edabd38e SB |
86 | void __init dove_ehci0_init(void) |
87 | { | |
72053353 | 88 | orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); |
edabd38e SB |
89 | } |
90 | ||
91 | /***************************************************************************** | |
92 | * EHCI1 | |
93 | ****************************************************************************/ | |
edabd38e SB |
94 | void __init dove_ehci1_init(void) |
95 | { | |
db33f4de | 96 | orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); |
edabd38e SB |
97 | } |
98 | ||
99 | /***************************************************************************** | |
100 | * GE00 | |
101 | ****************************************************************************/ | |
edabd38e SB |
102 | void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) |
103 | { | |
30e0f580 HR |
104 | orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, |
105 | IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR); | |
edabd38e SB |
106 | } |
107 | ||
108 | /***************************************************************************** | |
109 | * SoC RTC | |
110 | ****************************************************************************/ | |
edabd38e SB |
111 | void __init dove_rtc_init(void) |
112 | { | |
f6eaccb3 | 113 | orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); |
edabd38e SB |
114 | } |
115 | ||
116 | /***************************************************************************** | |
117 | * SATA | |
118 | ****************************************************************************/ | |
edabd38e SB |
119 | void __init dove_sata_init(struct mv_sata_platform_data *sata_data) |
120 | { | |
db33f4de | 121 | orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); |
9e613f8a | 122 | |
edabd38e SB |
123 | } |
124 | ||
125 | /***************************************************************************** | |
126 | * UART0 | |
127 | ****************************************************************************/ | |
edabd38e SB |
128 | void __init dove_uart0_init(void) |
129 | { | |
28a2b450 | 130 | orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, |
74c33576 | 131 | IRQ_DOVE_UART_0, tclk); |
edabd38e SB |
132 | } |
133 | ||
134 | /***************************************************************************** | |
135 | * UART1 | |
136 | ****************************************************************************/ | |
edabd38e SB |
137 | void __init dove_uart1_init(void) |
138 | { | |
28a2b450 | 139 | orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, |
74c33576 | 140 | IRQ_DOVE_UART_1, tclk); |
edabd38e SB |
141 | } |
142 | ||
143 | /***************************************************************************** | |
144 | * UART2 | |
145 | ****************************************************************************/ | |
edabd38e SB |
146 | void __init dove_uart2_init(void) |
147 | { | |
28a2b450 | 148 | orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, |
74c33576 | 149 | IRQ_DOVE_UART_2, tclk); |
edabd38e SB |
150 | } |
151 | ||
152 | /***************************************************************************** | |
153 | * UART3 | |
154 | ****************************************************************************/ | |
edabd38e SB |
155 | void __init dove_uart3_init(void) |
156 | { | |
28a2b450 | 157 | orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, |
74c33576 | 158 | IRQ_DOVE_UART_3, tclk); |
edabd38e SB |
159 | } |
160 | ||
161 | /***************************************************************************** | |
980f9f60 | 162 | * SPI |
edabd38e | 163 | ****************************************************************************/ |
edabd38e SB |
164 | void __init dove_spi0_init(void) |
165 | { | |
4574b886 | 166 | orion_spi_init(DOVE_SPI0_PHYS_BASE); |
edabd38e SB |
167 | } |
168 | ||
edabd38e SB |
169 | void __init dove_spi1_init(void) |
170 | { | |
4574b886 | 171 | orion_spi_1_init(DOVE_SPI1_PHYS_BASE); |
edabd38e SB |
172 | } |
173 | ||
174 | /***************************************************************************** | |
175 | * I2C | |
176 | ****************************************************************************/ | |
edabd38e SB |
177 | void __init dove_i2c_init(void) |
178 | { | |
aac7ffa3 | 179 | orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); |
edabd38e SB |
180 | } |
181 | ||
182 | /***************************************************************************** | |
183 | * Time handling | |
184 | ****************************************************************************/ | |
4ee1f6b5 LB |
185 | void __init dove_init_early(void) |
186 | { | |
187 | orion_time_set_base(TIMER_VIRT_BASE); | |
188 | } | |
189 | ||
edabd38e SB |
190 | static int get_tclk(void) |
191 | { | |
192 | /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */ | |
193 | return 166666667; | |
194 | } | |
195 | ||
ca2ac5cc | 196 | static void __init dove_timer_init(void) |
edabd38e | 197 | { |
4ee1f6b5 LB |
198 | orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, |
199 | IRQ_DOVE_BRIDGE, get_tclk()); | |
edabd38e SB |
200 | } |
201 | ||
202 | struct sys_timer dove_timer = { | |
203 | .init = dove_timer_init, | |
204 | }; | |
205 | ||
edabd38e SB |
206 | /***************************************************************************** |
207 | * XOR 0 | |
208 | ****************************************************************************/ | |
edabd38e SB |
209 | void __init dove_xor0_init(void) |
210 | { | |
db33f4de | 211 | orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, |
ee962723 | 212 | IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); |
edabd38e SB |
213 | } |
214 | ||
215 | /***************************************************************************** | |
216 | * XOR 1 | |
217 | ****************************************************************************/ | |
edabd38e SB |
218 | void __init dove_xor1_init(void) |
219 | { | |
ee962723 AL |
220 | orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, |
221 | IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); | |
edabd38e SB |
222 | } |
223 | ||
16bc90af SB |
224 | /***************************************************************************** |
225 | * SDIO | |
226 | ****************************************************************************/ | |
227 | static u64 sdio_dmamask = DMA_BIT_MASK(32); | |
228 | ||
229 | static struct resource dove_sdio0_resources[] = { | |
230 | { | |
231 | .start = DOVE_SDIO0_PHYS_BASE, | |
232 | .end = DOVE_SDIO0_PHYS_BASE + 0xff, | |
233 | .flags = IORESOURCE_MEM, | |
234 | }, { | |
235 | .start = IRQ_DOVE_SDIO0, | |
236 | .end = IRQ_DOVE_SDIO0, | |
237 | .flags = IORESOURCE_IRQ, | |
238 | }, | |
239 | }; | |
240 | ||
241 | static struct platform_device dove_sdio0 = { | |
930e2fe7 | 242 | .name = "sdhci-dove", |
16bc90af SB |
243 | .id = 0, |
244 | .dev = { | |
245 | .dma_mask = &sdio_dmamask, | |
246 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
247 | }, | |
248 | .resource = dove_sdio0_resources, | |
249 | .num_resources = ARRAY_SIZE(dove_sdio0_resources), | |
250 | }; | |
251 | ||
252 | void __init dove_sdio0_init(void) | |
253 | { | |
254 | platform_device_register(&dove_sdio0); | |
255 | } | |
256 | ||
257 | static struct resource dove_sdio1_resources[] = { | |
258 | { | |
259 | .start = DOVE_SDIO1_PHYS_BASE, | |
260 | .end = DOVE_SDIO1_PHYS_BASE + 0xff, | |
261 | .flags = IORESOURCE_MEM, | |
262 | }, { | |
263 | .start = IRQ_DOVE_SDIO1, | |
264 | .end = IRQ_DOVE_SDIO1, | |
265 | .flags = IORESOURCE_IRQ, | |
266 | }, | |
267 | }; | |
268 | ||
269 | static struct platform_device dove_sdio1 = { | |
930e2fe7 | 270 | .name = "sdhci-dove", |
16bc90af SB |
271 | .id = 1, |
272 | .dev = { | |
273 | .dma_mask = &sdio_dmamask, | |
274 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
275 | }, | |
276 | .resource = dove_sdio1_resources, | |
277 | .num_resources = ARRAY_SIZE(dove_sdio1_resources), | |
278 | }; | |
279 | ||
280 | void __init dove_sdio1_init(void) | |
281 | { | |
282 | platform_device_register(&dove_sdio1); | |
283 | } | |
284 | ||
edabd38e SB |
285 | void __init dove_init(void) |
286 | { | |
edabd38e | 287 | printk(KERN_INFO "Dove 88AP510 SoC, "); |
2f129bf4 | 288 | printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); |
edabd38e | 289 | |
573a652f LB |
290 | #ifdef CONFIG_CACHE_TAUROS2 |
291 | tauros2_init(); | |
292 | #endif | |
edabd38e SB |
293 | dove_setup_cpu_mbus(); |
294 | ||
2f129bf4 AL |
295 | /* Setup root of clk tree */ |
296 | clk_init(); | |
297 | ||
edabd38e SB |
298 | /* internal devices that every board has */ |
299 | dove_rtc_init(); | |
300 | dove_xor0_init(); | |
301 | dove_xor1_init(); | |
302 | } | |
6ca6ff97 RK |
303 | |
304 | void dove_restart(char mode, const char *cmd) | |
305 | { | |
306 | /* | |
307 | * Enable soft reset to assert RSTOUTn. | |
308 | */ | |
309 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); | |
310 | ||
311 | /* | |
312 | * Assert soft reset. | |
313 | */ | |
314 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); | |
315 | ||
316 | while (1) | |
317 | ; | |
318 | } |