[linux-2.6-block.git] / arch / arm / mach-davinci / sram.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * mach-davinci/sram.c - DaVinci simple SRAM allocator
 *
 * Copyright (C) 2009 David Brownell
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/genalloc.h>

#include <mach/common.h>
#include "sram.h"

static struct gen_pool *sram_pool;

struct gen_pool *sram_get_gen_pool(void)
{
	return sram_pool;
}

void *sram_alloc(size_t len, dma_addr_t *dma)
{
	dma_addr_t dma_base = davinci_soc_info.sram_dma;

	if (dma)
		*dma = 0;
	if (!sram_pool || (dma && !dma_base))
		return NULL;

	return gen_pool_dma_alloc(sram_pool, len, dma);

}
EXPORT_SYMBOL(sram_alloc);

void sram_free(void *addr, size_t len)
{
	gen_pool_free(sram_pool, (unsigned long) addr, len);
}
EXPORT_SYMBOL(sram_free);


/*
 * REVISIT This supports CPU and DMA access to/from SRAM, but it
 * doesn't (yet?) support some other notable uses of SRAM:  as TCM
 * for data and/or instructions; and holding code needed to enter
 * and exit suspend states (while DRAM can't be used).
 */
static int __init sram_init(void)
{
	phys_addr_t phys = davinci_soc_info.sram_dma;
	unsigned len = davinci_soc_info.sram_len;
	int status = 0;
	void __iomem *addr;

	if (len) {
		len = min_t(unsigned, len, SRAM_SIZE);
		sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1);
		if (!sram_pool)
			status = -ENOMEM;
	}

	if (sram_pool) {
		addr = ioremap(phys, len);
		if (!addr)
			return -ENOMEM;
		status = gen_pool_add_virt(sram_pool, (unsigned long) addr,
					   phys, len, -1);
		if (status < 0)
			iounmap(addr);
	}

	WARN_ON(status < 0);
	return status;
}
core_initcall(sram_init);
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
20e9969b DB	2	/*
	3	* mach-davinci/sram.c - DaVinci simple SRAM allocator
	4	*
	5	* Copyright (C) 2009 David Brownell
20e9969b DB	6	*/
20e9969b DB	7	#include <linux/module.h>
20e9969b	8	#include <linux/init.h>
626863a3	9	#include <linux/io.h>
20e9969b DB	10	#include <linux/genalloc.h>
	11
	12	#include <mach/common.h>
3acf731c	13	#include "sram.h"
20e9969b	14
20e9969b DB	15	static struct gen_pool *sram_pool;
20e9969b DB	16
983c42ba MP	17	struct gen_pool *sram_get_gen_pool(void)
	18	{
	19	return sram_pool;
	20	}
	21
20e9969b DB	22	void sram_alloc(size_t len, dma_addr_t dma)
20e9969b DB	23	{
20e9969b DB	24	dma_addr_t dma_base = davinci_soc_info.sram_dma;
	25
	26	if (dma)
	27	*dma = 0;
	28	if (!sram_pool \|\| (dma && !dma_base))
	29	return NULL;
	30
66f11969	31	return gen_pool_dma_alloc(sram_pool, len, dma);
20e9969b DB	32
	33	}
	34	EXPORT_SYMBOL(sram_alloc);
	35
	36	void sram_free(void *addr, size_t len)
	37	{
	38	gen_pool_free(sram_pool, (unsigned long) addr, len);
	39	}
	40	EXPORT_SYMBOL(sram_free);
	41
	42
	43	/*
	44	* REVISIT This supports CPU and DMA access to/from SRAM, but it
	45	* doesn't (yet?) support some other notable uses of SRAM: as TCM
	46	* for data and/or instructions; and holding code needed to enter
	47	* and exit suspend states (while DRAM can't be used).
	48	*/
	49	static int __init sram_init(void)
	50	{
626863a3	51	phys_addr_t phys = davinci_soc_info.sram_dma;
20e9969b DB	52	unsigned len = davinci_soc_info.sram_len;
20e9969b DB	53	int status = 0;
182e7961	54	void __iomem *addr;
20e9969b DB	55
20e9969b DB	56	if (len) {
1d3bba61	57	len = min_t(unsigned, len, SRAM_SIZE);
20e9969b DB	58	sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1);
	59	if (!sram_pool)
	60	status = -ENOMEM;
	61	}
626863a3 BG	62
	63	if (sram_pool) {
	64	addr = ioremap(phys, len);
	65	if (!addr)
	66	return -ENOMEM;
182e7961	67	status = gen_pool_add_virt(sram_pool, (unsigned long) addr,
626863a3 BG	68	phys, len, -1);
	69	if (status < 0)
	70	iounmap(addr);
	71	}
	72
20e9969b DB	73	WARN_ON(status < 0);
	74	return status;
	75	}
	76	core_initcall(sram_init);
	77