[linux-2.6-block.git] / arch / arm / mach-davinci / mux.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Utility to set the DAVINCI MUX register from a table in mux.h
 *
 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
 *
 * Based on linux/arch/arm/plat-omap/mux.c:
 * Copyright (C) 2003 - 2005 Nokia Corporation
 *
 * Written by Tony Lindgren
 *
 * 2007 (c) MontaVista Software, Inc.
 *
 * Copyright (C) 2008 Texas Instruments.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/io.h>
#include <linux/module.h>
#include <linux/spinlock.h>

#include "mux.h"
#include "common.h"

static void __iomem *pinmux_base;

/*
 * Sets the DAVINCI MUX register based on the table
 */
int davinci_cfg_reg(const unsigned long index)
{
	static DEFINE_SPINLOCK(mux_spin_lock);
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	unsigned long flags;
	const struct mux_config *cfg;
	unsigned int reg_orig = 0, reg = 0;
	unsigned int mask, warn = 0;

	if (WARN_ON(!soc_info->pinmux_pins))
		return -ENODEV;

	if (!pinmux_base) {
		pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
		if (WARN_ON(!pinmux_base))
			return -ENOMEM;
	}

	if (index >= soc_info->pinmux_pins_num) {
		pr_err("Invalid pin mux index: %lu (%lu)\n",
		       index, soc_info->pinmux_pins_num);
		dump_stack();
		return -ENODEV;
	}

	cfg = &soc_info->pinmux_pins[index];

	if (cfg->name == NULL) {
		pr_err("No entry for the specified index\n");
		return -ENODEV;
	}

	/* Update the mux register in question */
	if (cfg->mask) {
		unsigned	tmp1, tmp2;

		spin_lock_irqsave(&mux_spin_lock, flags);
		reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);

		mask = (cfg->mask << cfg->mask_offset);
		tmp1 = reg_orig & mask;
		reg = reg_orig & ~mask;

		tmp2 = (cfg->mode << cfg->mask_offset);
		reg |= tmp2;

		if (tmp1 != tmp2)
			warn = 1;

		__raw_writel(reg, pinmux_base + cfg->mux_reg);
		spin_unlock_irqrestore(&mux_spin_lock, flags);
	}

	if (warn) {
#ifdef CONFIG_DAVINCI_MUX_WARNINGS
		pr_warn("initialized %s\n", cfg->name);
#endif
	}

#ifdef CONFIG_DAVINCI_MUX_DEBUG
	if (cfg->debug || warn) {
		pr_warn("Setting register %s\n", cfg->name);
		pr_warn("   %s (0x%08x) = 0x%08x -> 0x%08x\n",
			cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
	}
#endif

	return 0;
}
Commit	Line	Data
0fdebc5e	1	// SPDX-License-Identifier: GPL-2.0-only
83f53220	2	/*
5526b3f7	3	* Utility to set the DAVINCI MUX register from a table in mux.h
83f53220 VB	4	*
	5	* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
	6	*
5526b3f7 KH	7	* Based on linux/arch/arm/plat-omap/mux.c:
	8	* Copyright (C) 2003 - 2005 Nokia Corporation
	9	*
	10	* Written by Tony Lindgren
	11	*
0fdebc5e	12	* 2007 (c) MontaVista Software, Inc.
5526b3f7 KH	13	*
5526b3f7 KH	14	* Copyright (C) 2008 Texas Instruments.
83f53220	15	*/
a7ca2bcf JP	16
	17	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	18
83f53220	19	#include <linux/io.h>
5526b3f7	20	#include <linux/module.h>
83f53220 VB	21	#include <linux/spinlock.h>
83f53220 VB	22
ca31807b AB	23	#include "mux.h"
ca31807b AB	24	#include "common.h"
83f53220	25
779b0d53 CC	26	static void __iomem *pinmux_base;
779b0d53 CC	27
5526b3f7 KH	28	/*
	29	* Sets the DAVINCI MUX register based on the table
	30	*/
31612d64	31	int davinci_cfg_reg(const unsigned long index)
83f53220	32	{
5526b3f7	33	static DEFINE_SPINLOCK(mux_spin_lock);
0e585952	34	struct davinci_soc_info *soc_info = &davinci_soc_info;
5526b3f7 KH	35	unsigned long flags;
	36	const struct mux_config *cfg;
	37	unsigned int reg_orig = 0, reg = 0;
	38	unsigned int mask, warn = 0;
	39
779b0d53 CC	40	if (WARN_ON(!soc_info->pinmux_pins))
	41	return -ENODEV;
	42
	43	if (!pinmux_base) {
	44	pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
	45	if (WARN_ON(!pinmux_base))
	46	return -ENOMEM;
	47	}
5526b3f7	48
0e585952	49	if (index >= soc_info->pinmux_pins_num) {
a7ca2bcf	50	pr_err("Invalid pin mux index: %lu (%lu)\n",
0e585952	51	index, soc_info->pinmux_pins_num);
5526b3f7 KH	52	dump_stack();
	53	return -ENODEV;
	54	}
	55
0e585952	56	cfg = &soc_info->pinmux_pins[index];
5526b3f7 KH	57
5526b3f7 KH	58	if (cfg->name == NULL) {
a7ca2bcf	59	pr_err("No entry for the specified index\n");
5526b3f7 KH	60	return -ENODEV;
	61	}
	62
	63	/* Update the mux register in question */
	64	if (cfg->mask) {
	65	unsigned tmp1, tmp2;
	66
	67	spin_lock_irqsave(&mux_spin_lock, flags);
779b0d53	68	reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
5526b3f7 KH	69
	70	mask = (cfg->mask << cfg->mask_offset);
	71	tmp1 = reg_orig & mask;
	72	reg = reg_orig & ~mask;
	73
	74	tmp2 = (cfg->mode << cfg->mask_offset);
	75	reg \|= tmp2;
	76
	77	if (tmp1 != tmp2)
	78	warn = 1;
	79
779b0d53	80	__raw_writel(reg, pinmux_base + cfg->mux_reg);
5526b3f7 KH	81	spin_unlock_irqrestore(&mux_spin_lock, flags);
	82	}
	83
	84	if (warn) {
	85	#ifdef CONFIG_DAVINCI_MUX_WARNINGS
a7ca2bcf	86	pr_warn("initialized %s\n", cfg->name);
5526b3f7 KH	87	#endif
5526b3f7 KH	88	}
83f53220	89
5526b3f7 KH	90	#ifdef CONFIG_DAVINCI_MUX_DEBUG
5526b3f7 KH	91	if (cfg->debug \|\| warn) {
a7ca2bcf JP	92	pr_warn("Setting register %s\n", cfg->name);
	93	pr_warn(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
	94	cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
83f53220	95	}
5526b3f7	96	#endif
83f53220	97
5526b3f7	98	return 0;
83f53220	99	}