[linux-2.6-block.git] / arch / arm / mach-davinci / mux.c

/*
 * Utility to set the DAVINCI MUX register from a table in mux.h
 *
 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
 *
 * Based on linux/arch/arm/plat-omap/mux.c:
 * Copyright (C) 2003 - 2005 Nokia Corporation
 *
 * Written by Tony Lindgren
 *
 * 2007 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright (C) 2008 Texas Instruments.
 */
#include <linux/io.h>
#include <linux/module.h>
#include <linux/spinlock.h>

#include <mach/hardware.h>
#include <mach/mux.h>
#include <mach/common.h>

/*
 * Sets the DAVINCI MUX register based on the table
 */
int __init_or_module davinci_cfg_reg(const unsigned long index)
{
	static DEFINE_SPINLOCK(mux_spin_lock);
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	void __iomem *base = soc_info->pinmux_base;
	unsigned long flags;
	const struct mux_config *cfg;
	unsigned int reg_orig = 0, reg = 0;
	unsigned int mask, warn = 0;

	if (!soc_info->pinmux_pins)
		BUG();

	if (index >= soc_info->pinmux_pins_num) {
		printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
		       index, soc_info->pinmux_pins_num);
		dump_stack();
		return -ENODEV;
	}

	cfg = &soc_info->pinmux_pins[index];

	if (cfg->name == NULL) {
		printk(KERN_ERR "No entry for the specified index\n");
		return -ENODEV;
	}

	/* Update the mux register in question */
	if (cfg->mask) {
		unsigned	tmp1, tmp2;

		spin_lock_irqsave(&mux_spin_lock, flags);
		reg_orig = __raw_readl(base + cfg->mux_reg);

		mask = (cfg->mask << cfg->mask_offset);
		tmp1 = reg_orig & mask;
		reg = reg_orig & ~mask;

		tmp2 = (cfg->mode << cfg->mask_offset);
		reg |= tmp2;

		if (tmp1 != tmp2)
			warn = 1;

		__raw_writel(reg, base + cfg->mux_reg);
		spin_unlock_irqrestore(&mux_spin_lock, flags);
	}

	if (warn) {
#ifdef CONFIG_DAVINCI_MUX_WARNINGS
		printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
#endif
	}

#ifdef CONFIG_DAVINCI_MUX_DEBUG
	if (cfg->debug || warn) {
		printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
		printk(KERN_WARNING "	   %s (0x%08x) = 0x%08x -> 0x%08x\n",
		       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
	}
#endif

	return 0;
}
EXPORT_SYMBOL(davinci_cfg_reg);
Commit	Line	Data
83f53220	1	/*
5526b3f7	2	* Utility to set the DAVINCI MUX register from a table in mux.h
83f53220 VB	3	*
	4	* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
	5	*
5526b3f7 KH	6	* Based on linux/arch/arm/plat-omap/mux.c:
	7	* Copyright (C) 2003 - 2005 Nokia Corporation
	8	*
	9	* Written by Tony Lindgren
	10	*
83f53220 VB	11	* 2007 (c) MontaVista Software, Inc. This file is licensed under
	12	* the terms of the GNU General Public License version 2. This program
	13	* is licensed "as is" without any warranty of any kind, whether express
	14	* or implied.
5526b3f7 KH	15	*
5526b3f7 KH	16	* Copyright (C) 2008 Texas Instruments.
83f53220 VB	17	*/
83f53220 VB	18	#include <linux/io.h>
5526b3f7	19	#include <linux/module.h>
83f53220 VB	20	#include <linux/spinlock.h>
83f53220 VB	21
a09e64fb	22	#include <mach/hardware.h>
a09e64fb	23	#include <mach/mux.h>
0e585952	24	#include <mach/common.h>
83f53220	25
5526b3f7 KH	26	/*
	27	* Sets the DAVINCI MUX register based on the table
	28	*/
	29	int __init_or_module davinci_cfg_reg(const unsigned long index)
83f53220	30	{
5526b3f7	31	static DEFINE_SPINLOCK(mux_spin_lock);
0e585952 MG	32	struct davinci_soc_info *soc_info = &davinci_soc_info;
0e585952 MG	33	void __iomem *base = soc_info->pinmux_base;
5526b3f7 KH	34	unsigned long flags;
	35	const struct mux_config *cfg;
	36	unsigned int reg_orig = 0, reg = 0;
	37	unsigned int mask, warn = 0;
	38
0e585952	39	if (!soc_info->pinmux_pins)
5526b3f7 KH	40	BUG();
5526b3f7 KH	41
0e585952	42	if (index >= soc_info->pinmux_pins_num) {
5526b3f7	43	printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
0e585952	44	index, soc_info->pinmux_pins_num);
5526b3f7 KH	45	dump_stack();
	46	return -ENODEV;
	47	}
	48
0e585952	49	cfg = &soc_info->pinmux_pins[index];
5526b3f7 KH	50
	51	if (cfg->name == NULL) {
	52	printk(KERN_ERR "No entry for the specified index\n");
	53	return -ENODEV;
	54	}
	55
	56	/* Update the mux register in question */
	57	if (cfg->mask) {
	58	unsigned tmp1, tmp2;
	59
	60	spin_lock_irqsave(&mux_spin_lock, flags);
	61	reg_orig = __raw_readl(base + cfg->mux_reg);
	62
	63	mask = (cfg->mask << cfg->mask_offset);
	64	tmp1 = reg_orig & mask;
	65	reg = reg_orig & ~mask;
	66
	67	tmp2 = (cfg->mode << cfg->mask_offset);
	68	reg \|= tmp2;
	69
	70	if (tmp1 != tmp2)
	71	warn = 1;
	72
	73	__raw_writel(reg, base + cfg->mux_reg);
	74	spin_unlock_irqrestore(&mux_spin_lock, flags);
	75	}
	76
	77	if (warn) {
	78	#ifdef CONFIG_DAVINCI_MUX_WARNINGS
	79	printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
	80	#endif
	81	}
83f53220	82
5526b3f7 KH	83	#ifdef CONFIG_DAVINCI_MUX_DEBUG
	84	if (cfg->debug \|\| warn) {
	85	printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
	86	printk(KERN_WARNING " %s (0x%08x) = 0x%08x -> 0x%08x\n",
	87	cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
83f53220	88	}
5526b3f7	89	#endif
83f53220	90
5526b3f7	91	return 0;
83f53220	92	}
5526b3f7	93	EXPORT_SYMBOL(davinci_cfg_reg);